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Wed, 25 May 2022 12:10:51 +0000 From: Dragan Mladjenovic To: Thomas Bogendoerfer Cc: Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Dragan Mladjenovic Subject: [PATCH v2 03/12] irqchip: mips-gic: Introduce gic_with_each_online_cpu() Date: Wed, 25 May 2022 14:10:21 +0200 Message-Id: <20220525121030.16054-4-Dragan.Mladjenovic@syrmia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> References: <20220525121030.16054-1-Dragan.Mladjenovic@syrmia.com> X-ClientProxiedBy: VE1PR08CA0031.eurprd08.prod.outlook.com (2603:10a6:803:104::44) To VI1PR03MB4208.eurprd03.prod.outlook.com (2603:10a6:803:51::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2d3f9628-bbb2-441a-d420-08da3e479c3e X-MS-TrafficTypeDiagnostic: AS8PR03MB7859:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4dXjUw2CzNK91TdbR7GXUUmDCxjcD7k0syb/3+Q16ZdXfEqQGzT99k7HCmV80nQb+2Yg8wjIIr9dvtH7XxVJqd4g6124RosfJ5Ui9LKYabXBQKvNLOwvETwz/4nLIik+Ysynsc5Dr7lxzLTpKHEzDTgoj7kEEI6Ha5MUDbmpqgoW3hub4VXPn8xhvhKIs6uZBF7lS5P0QkkxVYz/o/r0WECVDp/FYEZdtrPvepss2pXs3Xu0tWiixPxeA6zAe9aBY2NeczpL//omFkQRX0EaxunUwgesyOl9dZCvTU0NZqEtRGbt8XqvMK/jpQwKlKkdrdaxafdCTJd8Re8fae2Q+ZJf9ZYP90aSOQENEhmV4MnUSj7OlKGPYckA3uW4Ej7z6opIVP1+58irpIy0oxi9vuT4lXaf7H0Ykq5Db2jgEYxQ9hHHb7g57SaCtMgzga6eKvBFHxpE4T83VKxN71/uBsdpxo9h7b6sqkIWYEFMm8iy23Z43EKnuJIkTxqybluP6XbPCxZe6L3zyWPuiPqSFRdqRb34B25rzzSpkvmA9N5Bsg43Pu7TUKp9GESAGqdXqZVzpYYmD1gL4j1fFqPx5RedYwTdO5G+B18jutXmbXNnHrw2wUeujL0c/jOuAh6ucdtyq2Qvek9Yr6R3ktou+/E0mRx0sbpKvyLhXPt3jAfISI+vNBo0xuxMxEUJAfBL3KWj+JZC17vjYEfrtaN7pV8dmrWi2aUrk4dUp1FZY+7EVPYe8j6f1Ru/Bi0lL/5AiYCpINpb6AQQ6Vd/fm9mMvFeMVeNNuNrlA1jIxIXj5tT2s3lhQxfzsodb1NjyGPYyRuQonqXSa0XsDJCap+BZ3q45MAlnBV1NHlELFd6zunK0JdO0coGKzJmP1dLqKKOoW1km30M2JM1mG63cnPhVQ53T3VLtEm4NKb127LZWfIK7gHQwTojN9N6UcTRxh++tzXhwY/TnrwYF/d6BKt5tXZmY1Bx8Wc47NlcKtCdcoIl3llhSNTKMR42b5Yhd5Y5zX+CWqs5dPZEwTN3s0Yd9MKh3VeTC5Fm/58zfppRtBq4rDUbZvuwMiecV+NndgLQIKKM/oBVhmCqM4EskgMKpjZSWft4CPq5YoHLTsVhZ6lb6xXcZNpGSjfMd07E/Nm6YNwbjNjFWViKvbzOIYuBFjXi4pqYQJ4wiippu62CkBzYHQbL3MdABO2fyJ44/vJIVtrBLxnfKyyaDlGSSqO7k6BLW7g/PFIcF9NCeXOwDtCLh0futGjxghFw0bikdJzmp6F1oRam80JvysKm+Yu7J49YF5xbKd0Cncyuxw2VF5KVp/RzPjHrhZYlcnDzZql5J75KKaUWbVhHoiRzvahRMFo9nI2rbz+spdDXZA5x40Mws/fPuarPbr59FflGSKbBFdG4IJFHgMXsXwz+k9ipy1RXdNGOoi77W+PP7l+pzPa14HHlh0bZMKYUq0iaU/eHIFacz2UWTjA4dz4loEPDWU4MsYgLOnWNGTuTlPXVevGXdin52VHmb5dB7Vbncjp/r3QZijNL24XkttKzExuVEriRoJZcymjdbk5yaqczc8LKLFx+KEWCiDh4H4cHco23wUAVpnOjf/pEkCaBKBf7jCO6ZnFIV1XJLlwZrY+db/dMTJagYjPfC+SbV0VYLwOHd5CaBJu3H4HwfMwnoWen3zdkqIdWCeAhlZMIaEtsPK/HuMs94aYcdCtNF9SCuHHpAvhlIsh3ceC7ARKNnwbzEkJkCN0Ek2b1qsZmzpnq7MY= X-OriginatorOrg: syrmia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d3f9628-bbb2-441a-d420-08da3e479c3e X-MS-Exchange-CrossTenant-AuthSource: VI1PR03MB4208.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2022 12:10:51.3184 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: opIP3kUlevw0scumphav6/gVQaLnWuFJx4GV3cP9yB6OleBEeXJ5DLahiwaZs/rHYPd7DVPXDevCziC55wJ+WdTSXZb64QvjU6IhwtXJWb4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB7859 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Paul Burton A few pieces of code in the MIPS GIC driver operate on the GIC local register block for each online CPU, accessing each via the GIC's other/redirect register block. This patch abstracts the process of iterating over online CPUs & configuring the other/redirect region to access their registers through a new gic_with_each_online_cpu() macro. This simplifies users of the new macro slightly, and more importantly prepares us for handling multi-cluster systems where the register configuration will be done via the CM's GCR_CL_REDIRECT register. By abstracting all other/redirect block configuration through this macro, and the __gic_with_next_online_cpu() function which backs it, users will trivially gain support for multi-cluster when it is implemented in __gic_with_next_online_cpu(). Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index ff89b36267dd..4872bebe24cf 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -65,6 +65,45 @@ static struct gic_all_vpes_chip_data { bool mask; } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; +static int __gic_with_next_online_cpu(int prev) +{ + unsigned int cpu; + + /* Discover the next online CPU */ + cpu = cpumask_next(prev, cpu_online_mask); + + /* If there isn't one, we're done */ + if (cpu >= nr_cpu_ids) + return cpu; + + /* + * Lock access to the next CPU's GIC local register block. + * + * In the single cluster case we simply set GIC_VL_OTHER. The caller + * holds gic_lock so nothing can clobber the value we write. + */ + write_gic_vl_other(mips_cm_vp_id(cpu)); + + return cpu; +} + +/** + * gic_with_each_online_cpu() - Iterate over online CPUs, access local registers + * @cpu: An integer variable to hold the current CPU number + * + * Iterate over online CPUs & configure the other/redirect register region to + * access each CPUs GIC local register block, which can be accessed from the + * loop body using read_gic_vo_*() or write_gic_vo_*() accessor functions or + * their derivatives. + * + * The caller must hold gic_lock throughout the loop, such that GIC_VL_OTHER + * cannot be clobbered. + */ +#define gic_with_each_online_cpu(cpu) \ + for ((cpu) = __gic_with_next_online_cpu(-1); \ + (cpu) = __gic_with_next_online_cpu(cpu), \ + (cpu) < nr_cpu_ids;) + static void gic_clear_pcpu_masks(unsigned int intr) { unsigned int i; @@ -357,10 +396,8 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d) cd->mask = false; spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + gic_with_each_online_cpu(cpu) write_gic_vo_rmask(BIT(intr)); - } spin_unlock_irqrestore(&gic_lock, flags); } @@ -375,10 +412,8 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d) cd->mask = true; spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + gic_with_each_online_cpu(cpu) write_gic_vo_smask(BIT(intr)); - } spin_unlock_irqrestore(&gic_lock, flags); } @@ -532,10 +567,8 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, return -EPERM; spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + gic_with_each_online_cpu(cpu) write_gic_vo_map(mips_gic_vx_map_reg(intr), map); - } spin_unlock_irqrestore(&gic_lock, flags); return 0;