| Message ID | 20220708160244.21933-8-aidanmacdonald.0x0@gmail.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | ASoC: cleanups and improvements for jz4740-i2s | expand |
Hi Aidan, On 2022/7/9 上午12:02, Aidan MacDonald wrote: > On some Ingenic SoCs, such as the X1000, there is a programmable > divider used to generate the I2S system clock from a PLL, rather > than a fixed PLL/2 clock. It doesn't make much sense to call the > clock "pll half" on those SoCs, so the clock name should really be > a SoC-dependent value. > > Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> > --- > sound/soc/jz4740/jz4740-i2s.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c > index 0dcc658b3784..a41398c24d0e 100644 > --- a/sound/soc/jz4740/jz4740-i2s.c > +++ b/sound/soc/jz4740/jz4740-i2s.c > @@ -75,6 +75,8 @@ struct i2s_soc_info { > struct reg_field field_i2sdiv_capture; > struct reg_field field_i2sdiv_playback; > > + const char *pll_clk_name; > + > bool shared_fifo_flush; > }; > > @@ -281,7 +283,7 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, > clk_set_parent(i2s->clk_i2s, parent); > break; > case JZ4740_I2S_CLKSRC_PLL: > - parent = clk_get(NULL, "pll half"); > + parent = clk_get(NULL, i2s->soc_info->pll_clk_name); > if (IS_ERR(parent)) > return PTR_ERR(parent); > clk_set_parent(i2s->clk_i2s, parent); > @@ -400,6 +402,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info = { > .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), > .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > + .pll_clk_name = "pll half", > .shared_fifo_flush = true, > }; > > @@ -409,6 +412,7 @@ static const struct i2s_soc_info jz4760_i2s_soc_info = { > .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), > .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > + .pll_clk_name = "pll half", > }; Since JZ4760, according to the description of the I2SCDR register, Ingenic SoCs no longer use PLL/2 clock, but directly use PLL clock, so it seems also inappropriate to use "pll half" for these SoCs. > > static struct snd_soc_dai_driver jz4770_i2s_dai = { > @@ -435,6 +439,7 @@ static const struct i2s_soc_info jz4770_i2s_soc_info = { > .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), > .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), > .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > + .pll_clk_name = "pll half", > }; Same here. > > static const struct i2s_soc_info jz4780_i2s_soc_info = { > @@ -443,6 +448,7 @@ static const struct i2s_soc_info jz4780_i2s_soc_info = { > .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), > .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), > .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > + .pll_clk_name = "pll half", > }; > Same here. Thanks and best regards! > static const struct snd_soc_component_driver jz4740_i2s_component = {
Hi Zhou, Le mer., juil. 13 2022 at 22:33:44 +0800, Zhou Yanjie <zhouyu@wanyeetech.com> a écrit : > Hi Aidan, > > On 2022/7/9 上午12:02, Aidan MacDonald wrote: >> On some Ingenic SoCs, such as the X1000, there is a programmable >> divider used to generate the I2S system clock from a PLL, rather >> than a fixed PLL/2 clock. It doesn't make much sense to call the >> clock "pll half" on those SoCs, so the clock name should really be >> a SoC-dependent value. >> >> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> >> --- >> sound/soc/jz4740/jz4740-i2s.c | 8 +++++++- >> 1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/sound/soc/jz4740/jz4740-i2s.c >> b/sound/soc/jz4740/jz4740-i2s.c >> index 0dcc658b3784..a41398c24d0e 100644 >> --- a/sound/soc/jz4740/jz4740-i2s.c >> +++ b/sound/soc/jz4740/jz4740-i2s.c >> @@ -75,6 +75,8 @@ struct i2s_soc_info { >> struct reg_field field_i2sdiv_capture; >> struct reg_field field_i2sdiv_playback; >> + const char *pll_clk_name; >> + >> bool shared_fifo_flush; >> }; >> @@ -281,7 +283,7 @@ static int jz4740_i2s_set_sysclk(struct >> snd_soc_dai *dai, int clk_id, >> clk_set_parent(i2s->clk_i2s, parent); >> break; >> case JZ4740_I2S_CLKSRC_PLL: >> - parent = clk_get(NULL, "pll half"); >> + parent = clk_get(NULL, i2s->soc_info->pll_clk_name); >> if (IS_ERR(parent)) >> return PTR_ERR(parent); >> clk_set_parent(i2s->clk_i2s, parent); >> @@ -400,6 +402,7 @@ static const struct i2s_soc_info >> jz4740_i2s_soc_info = { >> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), >> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name = "pll half", >> .shared_fifo_flush = true, >> }; >> @@ -409,6 +412,7 @@ static const struct i2s_soc_info >> jz4760_i2s_soc_info = { >> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name = "pll half", >> }; > > > Since JZ4760, according to the description of the I2SCDR register, > Ingenic SoCs no longer use PLL/2 clock, but directly use PLL clock, > so it seems also inappropriate to use "pll half" for these SoCs. The device tree passes the clock as "pll half". So the driver should use this name as well... Cheers, -Paul >> static struct snd_soc_dai_driver jz4770_i2s_dai = { >> @@ -435,6 +439,7 @@ static const struct i2s_soc_info >> jz4770_i2s_soc_info = { >> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), >> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name = "pll half", >> }; > > > Same here. > > >> static const struct i2s_soc_info jz4780_i2s_soc_info = { >> @@ -443,6 +448,7 @@ static const struct i2s_soc_info >> jz4780_i2s_soc_info = { >> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), >> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name = "pll half", >> }; >> > > Same here. > > > Thanks and best regards! > > >> static const struct snd_soc_component_driver jz4740_i2s_component >> = {
Hi Paul, On 2022/7/13 下午11:07, Paul Cercueil wrote: > Hi Zhou, > > Le mer., juil. 13 2022 at 22:33:44 +0800, Zhou Yanjie > <zhouyu@wanyeetech.com> a écrit : >> Hi Aidan, >> >> On 2022/7/9 上午12:02, Aidan MacDonald wrote: >>> On some Ingenic SoCs, such as the X1000, there is a programmable >>> divider used to generate the I2S system clock from a PLL, rather >>> than a fixed PLL/2 clock. It doesn't make much sense to call the >>> clock "pll half" on those SoCs, so the clock name should really be >>> a SoC-dependent value. >>> >>> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> >>> --- >>> sound/soc/jz4740/jz4740-i2s.c | 8 +++++++- >>> 1 file changed, 7 insertions(+), 1 deletion(-) >>> >>> diff --git a/sound/soc/jz4740/jz4740-i2s.c >>> b/sound/soc/jz4740/jz4740-i2s.c >>> index 0dcc658b3784..a41398c24d0e 100644 >>> --- a/sound/soc/jz4740/jz4740-i2s.c >>> +++ b/sound/soc/jz4740/jz4740-i2s.c >>> @@ -75,6 +75,8 @@ struct i2s_soc_info { >>> struct reg_field field_i2sdiv_capture; >>> struct reg_field field_i2sdiv_playback; >>> + const char *pll_clk_name; >>> + >>> bool shared_fifo_flush; >>> }; >>> @@ -281,7 +283,7 @@ static int jz4740_i2s_set_sysclk(struct >>> snd_soc_dai *dai, int clk_id, >>> clk_set_parent(i2s->clk_i2s, parent); >>> break; >>> case JZ4740_I2S_CLKSRC_PLL: >>> - parent = clk_get(NULL, "pll half"); >>> + parent = clk_get(NULL, i2s->soc_info->pll_clk_name); >>> if (IS_ERR(parent)) >>> return PTR_ERR(parent); >>> clk_set_parent(i2s->clk_i2s, parent); >>> @@ -400,6 +402,7 @@ static const struct i2s_soc_info >>> jz4740_i2s_soc_info = { >>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), >>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>> + .pll_clk_name = "pll half", >>> .shared_fifo_flush = true, >>> }; >>> @@ -409,6 +412,7 @@ static const struct i2s_soc_info >>> jz4760_i2s_soc_info = { >>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>> + .pll_clk_name = "pll half", >>> }; >> >> >> Since JZ4760, according to the description of the I2SCDR register, >> Ingenic SoCs no longer use PLL/2 clock, but directly use PLL clock, >> so it seems also inappropriate to use "pll half" for these SoCs. > > The device tree passes the clock as "pll half". So the driver should > use this name as well... I see... It seems that the device tree of JZ4770 has used "pll half" already, but there is no "pll half" used anywhere in the device tree of JZ4780, maybe we can keep the pll_clk_name of JZ4770 as "pll half", and change the pll_clk_name of JZ4780 to a more reasonable name. Thanks and best regards! > > Cheers, > -Paul > >>> static struct snd_soc_dai_driver jz4770_i2s_dai = { >>> @@ -435,6 +439,7 @@ static const struct i2s_soc_info >>> jz4770_i2s_soc_info = { >>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), >>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>> + .pll_clk_name = "pll half", >>> }; >> >> >> Same here. >> >> >>> static const struct i2s_soc_info jz4780_i2s_soc_info = { >>> @@ -443,6 +448,7 @@ static const struct i2s_soc_info >>> jz4780_i2s_soc_info = { >>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), >>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>> + .pll_clk_name = "pll half", >>> }; >>> >> >> Same here. >> >> >> Thanks and best regards! >> >> >>> static const struct snd_soc_component_driver jz4740_i2s_component = { >
Hi Aidan, Le ven., juil. 8 2022 at 17:02:40 +0100, Aidan MacDonald <aidanmacdonald.0x0@gmail.com> a écrit : > On some Ingenic SoCs, such as the X1000, there is a programmable > divider used to generate the I2S system clock from a PLL, rather > than a fixed PLL/2 clock. It doesn't make much sense to call the > clock "pll half" on those SoCs, so the clock name should really be > a SoC-dependent value. > > Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Cheers, -Paul > --- > sound/soc/jz4740/jz4740-i2s.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/sound/soc/jz4740/jz4740-i2s.c > b/sound/soc/jz4740/jz4740-i2s.c > index 0dcc658b3784..a41398c24d0e 100644 > --- a/sound/soc/jz4740/jz4740-i2s.c > +++ b/sound/soc/jz4740/jz4740-i2s.c > @@ -75,6 +75,8 @@ struct i2s_soc_info { > struct reg_field field_i2sdiv_capture; > struct reg_field field_i2sdiv_playback; > > + const char *pll_clk_name; > + > bool shared_fifo_flush; > }; > > @@ -281,7 +283,7 @@ static int jz4740_i2s_set_sysclk(struct > snd_soc_dai *dai, int clk_id, > clk_set_parent(i2s->clk_i2s, parent); > break; > case JZ4740_I2S_CLKSRC_PLL: > - parent = clk_get(NULL, "pll half"); > + parent = clk_get(NULL, i2s->soc_info->pll_clk_name); > if (IS_ERR(parent)) > return PTR_ERR(parent); > clk_set_parent(i2s->clk_i2s, parent); > @@ -400,6 +402,7 @@ static const struct i2s_soc_info > jz4740_i2s_soc_info = { > .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), > .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > + .pll_clk_name = "pll half", > .shared_fifo_flush = true, > }; > > @@ -409,6 +412,7 @@ static const struct i2s_soc_info > jz4760_i2s_soc_info = { > .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), > .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > + .pll_clk_name = "pll half", > }; > > static struct snd_soc_dai_driver jz4770_i2s_dai = { > @@ -435,6 +439,7 @@ static const struct i2s_soc_info > jz4770_i2s_soc_info = { > .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), > .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), > .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > + .pll_clk_name = "pll half", > }; > > static const struct i2s_soc_info jz4780_i2s_soc_info = { > @@ -443,6 +448,7 @@ static const struct i2s_soc_info > jz4780_i2s_soc_info = { > .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), > .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), > .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), > + .pll_clk_name = "pll half", > }; > > static const struct snd_soc_component_driver jz4740_i2s_component = { > -- > 2.35.1 >
Zhou Yanjie <zhouyu@wanyeetech.com> writes: > Hi Paul, > > On 2022/7/13 下午11:07, Paul Cercueil wrote: >> Hi Zhou, >> >> Le mer., juil. 13 2022 at 22:33:44 +0800, Zhou Yanjie <zhouyu@wanyeetech.com> >> a écrit : >>> Hi Aidan, >>> >>> On 2022/7/9 上午12:02, Aidan MacDonald wrote: >>>> @@ -400,6 +402,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info = >>>> { >>>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), >>>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>>> + .pll_clk_name = "pll half", >>>> .shared_fifo_flush = true, >>>> }; >>> >>> >>> Since JZ4760, according to the description of the I2SCDR register, >>> Ingenic SoCs no longer use PLL/2 clock, but directly use PLL clock, >>> so it seems also inappropriate to use "pll half" for these SoCs. >> >> The device tree passes the clock as "pll half". So the driver should use this >> name as well... > > > I see... > > It seems that the device tree of JZ4770 has used "pll half" already, > but there is no "pll half" used anywhere in the device tree of JZ4780, > maybe we can keep the pll_clk_name of JZ4770 as "pll half", and change > the pll_clk_name of JZ4780 to a more reasonable name. > > > Thanks and best regards! Actually, the clock names in the DT are meaningless. The clk_get() call matches only the clock's name in the CGU driver. So in fact the driver is "broken" for jz4780. It seems jz4770 doesn't work correctly either, it has no "pll half", and three possible parents for its "i2s" clock. Since the driver only supports the internal codec, which requires the "ext" clock, there isn't a problem in practice. I'm just going to drop this patch and leave .set_sysclk() alone for now. I think a better approach is to have the DT define an array of parent clocks for .set_sysclk()'s use, instead of hardcoding parents in the driver. If the parent array is missing the driver can default to using "ext" so existing DTs will work. Regards, Aidan
Hi Aidan, Le sam. 22 oct. 2022 à 18:15:05 +0100, Aidan MacDonald <aidanmacdonald.0x0@gmail.com> a écrit : > > Zhou Yanjie <zhouyu@wanyeetech.com> writes: > >> Hi Paul, >> >> On 2022/7/13 下午11:07, Paul Cercueil wrote: >>> Hi Zhou, >>> >>> Le mer., juil. 13 2022 at 22:33:44 +0800, Zhou Yanjie >>> <zhouyu@wanyeetech.com> >>> a écrit : >>>> Hi Aidan, >>>> >>>> On 2022/7/9 上午12:02, Aidan MacDonald wrote: >>>>> @@ -400,6 +402,7 @@ static const struct i2s_soc_info >>>>> jz4740_i2s_soc_info = >>>>> { >>>>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, >>>>> 11), >>>>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, >>>>> 0, 3), >>>>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, >>>>> 0, 3), >>>>> + .pll_clk_name = "pll half", >>>>> .shared_fifo_flush = true, >>>>> }; >>>> >>>> >>>> Since JZ4760, according to the description of the I2SCDR register, >>>> Ingenic SoCs no longer use PLL/2 clock, but directly use PLL >>>> clock, >>>> so it seems also inappropriate to use "pll half" for these SoCs. >>> >>> The device tree passes the clock as "pll half". So the driver >>> should use this >>> name as well... >> >> >> I see... >> >> It seems that the device tree of JZ4770 has used "pll half" already, >> but there is no "pll half" used anywhere in the device tree of >> JZ4780, >> maybe we can keep the pll_clk_name of JZ4770 as "pll half", and >> change >> the pll_clk_name of JZ4780 to a more reasonable name. >> >> >> Thanks and best regards! > > Actually, the clock names in the DT are meaningless. The clk_get() > call > matches only the clock's name in the CGU driver. So in fact the driver > is "broken" for jz4780. It seems jz4770 doesn't work correctly either, > it has no "pll half", and three possible parents for its "i2s" clock. That's not true. The clock names are matched via DT. Only in the case where a corresponding clock cannot be found via DT will it search for the clock name among the clock providers. I believe this is a legacy mechanism and you absolutely shouldn't rely on it. -Paul > Since the driver only supports the internal codec, which requires the > "ext" clock, there isn't a problem in practice. > > I'm just going to drop this patch and leave .set_sysclk() alone for > now. > I think a better approach is to have the DT define an array of parent > clocks for .set_sysclk()'s use, instead of hardcoding parents in the > driver. If the parent array is missing the driver can default to using > "ext" so existing DTs will work. > > Regards, > Aidan
Paul Cercueil <paul@crapouillou.net> writes: > Hi Aidan, > > Le sam. 22 oct. 2022 à 18:15:05 +0100, Aidan MacDonald > <aidanmacdonald.0x0@gmail.com> a écrit : >> Zhou Yanjie <zhouyu@wanyeetech.com> writes: >> >>> Hi Paul, >>> On 2022/7/13 下午11:07, Paul Cercueil wrote: >>>> Hi Zhou, >>>> Le mer., juil. 13 2022 at 22:33:44 +0800, Zhou Yanjie >>>> <zhouyu@wanyeetech.com> >>>> a écrit : >>>>> Hi Aidan, >>>>> On 2022/7/9 上午12:02, Aidan MacDonald wrote: >>>>>> @@ -400,6 +402,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info >>>>>> = >>>>>> { >>>>>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), >>>>>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>>>>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>>>>> + .pll_clk_name = "pll half", >>>>>> .shared_fifo_flush = true, >>>>>> }; >>>>> Since JZ4760, according to the description of the I2SCDR register, >>>>> Ingenic SoCs no longer use PLL/2 clock, but directly use PLL clock, >>>>> so it seems also inappropriate to use "pll half" for these SoCs. >>>> The device tree passes the clock as "pll half". So the driver should use >>>> this >>>> name as well... >>> I see... >>> It seems that the device tree of JZ4770 has used "pll half" already, >>> but there is no "pll half" used anywhere in the device tree of JZ4780, >>> maybe we can keep the pll_clk_name of JZ4770 as "pll half", and change >>> the pll_clk_name of JZ4780 to a more reasonable name. >>> Thanks and best regards! >> Actually, the clock names in the DT are meaningless. The clk_get() call >> matches only the clock's name in the CGU driver. So in fact the driver >> is "broken" for jz4780. It seems jz4770 doesn't work correctly either, >> it has no "pll half", and three possible parents for its "i2s" clock. > > That's not true. The clock names are matched via DT. > > Only in the case where a corresponding clock cannot be found via DT will it > search for the clock name among the clock providers. I believe this is a legacy > mechanism and you absolutely shouldn't rely on it. > > -Paul > What you say is only true for clk_get() with a device argument. When the device argument is NULL -- which is the case in .set_sysclk() -- then the DT name is not matched. Check drivers/clk/clkdev.c, in clk_find(). When the dev_id is NULL, it will not match any lookup entries with a non-null dev_id, and I believe dev_id is the mechanism that implements DT clock lookup. Only the wildcard entries from the CGU driver will be matched if dev_id is NULL, so the DT is being ignored. If you don't believe me, try changing "pll half" in the device tree and the I2S driver to something else. I have done this, and it doesn't work. That proves the name in the device tree is not being used. I agree we shouldn't rely on this, it's a legacy behavior, but the fact is that's how the driver already works. I'm dropping this patch because the driver is wrong and needs a different fix... >> I think a better approach is to have the DT define an array of parent >> clocks for .set_sysclk()'s use, instead of hardcoding parents in the >> driver. If the parent array is missing the driver can default to using >> "ext" so existing DTs will work. As much as I like this idea there doesn't seem to be a mechanism for handling a free-floating array of clocks in the DT. Everything has to be put in the main "clocks" array. That makes it pretty hard to figure out which ones are meant to be the parent clocks. Do you know of any way to do this generically from the DT? If there's no way to get away from a hardcoded array of names in the driver, I can at least add a device argument to clk_get() so it'll use the DT names. Regards, Aidan
Hi Aidan, Le dim. 23 oct. 2022 à 14:29:24 +0100, Aidan MacDonald <aidanmacdonald.0x0@gmail.com> a écrit : > > Paul Cercueil <paul@crapouillou.net> writes: > >> Hi Aidan, >> >> Le sam. 22 oct. 2022 à 18:15:05 +0100, Aidan MacDonald >> <aidanmacdonald.0x0@gmail.com> a écrit : >>> Zhou Yanjie <zhouyu@wanyeetech.com> writes: >>> >>>> Hi Paul, >>>> On 2022/7/13 下午11:07, Paul Cercueil wrote: >>>>> Hi Zhou, >>>>> Le mer., juil. 13 2022 at 22:33:44 +0800, Zhou Yanjie >>>>> <zhouyu@wanyeetech.com> >>>>> a écrit : >>>>>> Hi Aidan, >>>>>> On 2022/7/9 上午12:02, Aidan MacDonald wrote: >>>>>>> @@ -400,6 +402,7 @@ static const struct i2s_soc_info >>>>>>> jz4740_i2s_soc_info >>>>>>> = >>>>>>> { >>>>>>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, >>>>>>> 8, 11), >>>>>>> .field_i2sdiv_capture = >>>>>>> REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>>>>>> .field_i2sdiv_playback = >>>>>>> REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >>>>>>> + .pll_clk_name = "pll half", >>>>>>> .shared_fifo_flush = true, >>>>>>> }; >>>>>> Since JZ4760, according to the description of the I2SCDR >>>>>> register, >>>>>> Ingenic SoCs no longer use PLL/2 clock, but directly use PLL >>>>>> clock, >>>>>> so it seems also inappropriate to use "pll half" for these >>>>>> SoCs. >>>>> The device tree passes the clock as "pll half". So the driver >>>>> should use >>>>> this >>>>> name as well... >>>> I see... >>>> It seems that the device tree of JZ4770 has used "pll half" >>>> already, >>>> but there is no "pll half" used anywhere in the device tree of >>>> JZ4780, >>>> maybe we can keep the pll_clk_name of JZ4770 as "pll half", and >>>> change >>>> the pll_clk_name of JZ4780 to a more reasonable name. >>>> Thanks and best regards! >>> Actually, the clock names in the DT are meaningless. The clk_get() >>> call >>> matches only the clock's name in the CGU driver. So in fact the >>> driver >>> is "broken" for jz4780. It seems jz4770 doesn't work correctly >>> either, >>> it has no "pll half", and three possible parents for its "i2s" >>> clock. >> >> That's not true. The clock names are matched via DT. >> >> Only in the case where a corresponding clock cannot be found via DT >> will it >> search for the clock name among the clock providers. I believe this >> is a legacy >> mechanism and you absolutely shouldn't rely on it. >> >> -Paul >> > > What you say is only true for clk_get() with a device argument. When > the > device argument is NULL -- which is the case in .set_sysclk() -- then > the DT name is not matched. Check drivers/clk/clkdev.c, in clk_find(). > When the dev_id is NULL, it will not match any lookup entries with a > non-null dev_id, and I believe dev_id is the mechanism that implements > DT clock lookup. Only the wildcard entries from the CGU driver will be > matched if dev_id is NULL, so the DT is being ignored. > > If you don't believe me, try changing "pll half" in the device tree > and > the I2S driver to something else. I have done this, and it doesn't > work. > That proves the name in the device tree is not being used. Well, let's pass them a device pointer then. > I agree we shouldn't rely on this, it's a legacy behavior, but the > fact > is that's how the driver already works. I'm dropping this patch > because > the driver is wrong and needs a different fix... "How the driver already works" is a bit misleading, I never saw this .set_sysclk() callback being called, so I can't really say that it works. >>> I think a better approach is to have the DT define an array of >>> parent >>> clocks for .set_sysclk()'s use, instead of hardcoding parents in >>> the >>> driver. If the parent array is missing the driver can default to >>> using >>> "ext" so existing DTs will work. > > As much as I like this idea there doesn't seem to be a mechanism for > handling a free-floating array of clocks in the DT. Everything has > to be put in the main "clocks" array. That makes it pretty hard to > figure out which ones are meant to be the parent clocks. > > Do you know of any way to do this generically from the DT? If there's > no way to get away from a hardcoded array of names in the driver, I > can > at least add a device argument to clk_get() so it'll use the DT names. In jz4740_i2s_set_sysclk(): #define JZ4740_I2S_FIRST_PARENT_CLK 2 parent = of_clk_get(dev->of_node, JZ4740_I2S_FIRST_PARENT_CLK + clk_id); is how I'd do it. The DTs all have "aic", "i2s" as the first two clocks. It is even enforced in the DT schemas. Cheers, -Paul
Paul Cercueil <paul@crapouillou.net> writes: > Hi Aidan, > > Le dim. 23 oct. 2022 à 14:29:24 +0100, Aidan MacDonald > <aidanmacdonald.0x0@gmail.com> a écrit : >> Paul Cercueil <paul@crapouillou.net> writes: >> >>> Hi Aidan, >>> Le sam. 22 oct. 2022 à 18:15:05 +0100, Aidan MacDonald >>> <aidanmacdonald.0x0@gmail.com> a écrit : >>>> Actually, the clock names in the DT are meaningless. The clk_get() call >>>> matches only the clock's name in the CGU driver. So in fact the driver >>>> is "broken" for jz4780. It seems jz4770 doesn't work correctly either, >>>> it has no "pll half", and three possible parents for its "i2s" clock. >>> That's not true. The clock names are matched via DT. >>> Only in the case where a corresponding clock cannot be found via DT will it >>> search for the clock name among the clock providers. I believe this is a >>> legacy >>> mechanism and you absolutely shouldn't rely on it. >>> -Paul >>> >> What you say is only true for clk_get() with a device argument. When the >> device argument is NULL -- which is the case in .set_sysclk() -- then >> the DT name is not matched. Check drivers/clk/clkdev.c, in clk_find(). >> When the dev_id is NULL, it will not match any lookup entries with a >> non-null dev_id, and I believe dev_id is the mechanism that implements >> DT clock lookup. Only the wildcard entries from the CGU driver will be >> matched if dev_id is NULL, so the DT is being ignored. >> If you don't believe me, try changing "pll half" in the device tree and >> the I2S driver to something else. I have done this, and it doesn't work. >> That proves the name in the device tree is not being used. > > Well, let's pass them a device pointer then. > Yes, I'll do that when I revise the patch. >> I agree we shouldn't rely on this, it's a legacy behavior, but the fact >> is that's how the driver already works. I'm dropping this patch because >> the driver is wrong and needs a different fix... > > "How the driver already works" is a bit misleading, I never saw this > .set_sysclk() callback being called, so I can't really say that it works. > >>>> I think a better approach is to have the DT define an array of parent >>>> clocks for .set_sysclk()'s use, instead of hardcoding parents in the >>>> driver. If the parent array is missing the driver can default to using >>>> "ext" so existing DTs will work. >> As much as I like this idea there doesn't seem to be a mechanism for >> handling a free-floating array of clocks in the DT. Everything has >> to be put in the main "clocks" array. That makes it pretty hard to >> figure out which ones are meant to be the parent clocks. >> Do you know of any way to do this generically from the DT? If there's >> no way to get away from a hardcoded array of names in the driver, I can >> at least add a device argument to clk_get() so it'll use the DT names. > > In jz4740_i2s_set_sysclk(): > > #define JZ4740_I2S_FIRST_PARENT_CLK 2 > parent = of_clk_get(dev->of_node, JZ4740_I2S_FIRST_PARENT_CLK + clk_id); > > is how I'd do it. > > The DTs all have "aic", "i2s" as the first two clocks. It is even enforced in > the DT schemas. > > Cheers, > -Paul Sounds like a plan. I was hoping to avoid adding CONFIG_OF back considering I removed it in an earlier patch since it was unused. :) Guess it doesn't really matter for this driver since the Ingenic SoCs need CONFIG_OF anyway. Regards, Aidan
diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 0dcc658b3784..a41398c24d0e 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -75,6 +75,8 @@ struct i2s_soc_info { struct reg_field field_i2sdiv_capture; struct reg_field field_i2sdiv_playback; + const char *pll_clk_name; + bool shared_fifo_flush; }; @@ -281,7 +283,7 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, clk_set_parent(i2s->clk_i2s, parent); break; case JZ4740_I2S_CLKSRC_PLL: - parent = clk_get(NULL, "pll half"); + parent = clk_get(NULL, i2s->soc_info->pll_clk_name); if (IS_ERR(parent)) return PTR_ERR(parent); clk_set_parent(i2s->clk_i2s, parent); @@ -400,6 +402,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", .shared_fifo_flush = true, }; @@ -409,6 +412,7 @@ static const struct i2s_soc_info jz4760_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", }; static struct snd_soc_dai_driver jz4770_i2s_dai = { @@ -435,6 +439,7 @@ static const struct i2s_soc_info jz4770_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", }; static const struct i2s_soc_info jz4780_i2s_soc_info = { @@ -443,6 +448,7 @@ static const struct i2s_soc_info jz4780_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", }; static const struct snd_soc_component_driver jz4740_i2s_component = {
On some Ingenic SoCs, such as the X1000, there is a programmable divider used to generate the I2S system clock from a PLL, rather than a fixed PLL/2 clock. It doesn't make much sense to call the clock "pll half" on those SoCs, so the clock name should really be a SoC-dependent value. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> --- sound/soc/jz4740/jz4740-i2s.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)