From patchwork Sat Oct 22 19:13:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24887C3A59D for ; Sat, 22 Oct 2022 19:13:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229921AbiJVTNZ (ORCPT ); Sat, 22 Oct 2022 15:13:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229875AbiJVTNZ (ORCPT ); Sat, 22 Oct 2022 15:13:25 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4017A75CE1; Sat, 22 Oct 2022 12:13:23 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id v130-20020a1cac88000000b003bcde03bd44so7342807wme.5; Sat, 22 Oct 2022 12:13:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MY6IyPLb8byubV16BAqKYfhJcNAg3mb02MFq86iJwT8=; b=mNh58tgRVR2/wTmW2aZ5EAeKLmKiiVaQktRA5/Ib6PWHVeJHCQ6G+4qDhGm8YgxXTL KbVYcinF6CCMgVdFX6oKLyRv7LZsoOY/CSE/Wt9yfUpQmHbVUyWMHIebKvERSBFv1o10 gSo2S+fizOcZCR9he73pDwJ8uT3QNyfvTKn0Wga0O1gDUpsKczTlaPeTBfmufI79YSjy 3DjG8njxZZHi9s2QH20GzWo4sck3fM11hgS1A05UadnhX6yi6pKpnOamRiux7km0zlsJ sbitFNzlj0WKco3d4UfOYCt6JCQHkGuURKfbJ0NRb+Z29UpyriRKLrzgjQCEx5bFYa5m 9kZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MY6IyPLb8byubV16BAqKYfhJcNAg3mb02MFq86iJwT8=; b=ftQ3Id67/SpmSzEdnTT5s6jQRi4RdXRjOwHCxaKr6r/geI6hN/Sj8VWJvoBsFo1Sj4 8BMqGNZvqtfyNQQcUKOL+9eJumxfXsW5urdNihgVm6hGC9ajXLnxJuRWTF9PGEhPxczs RMWrFHtAmBb8IvWdk9AvsXnWW+PcH5L96y89Ex18FCdHHcRkZ3bqE564edUokjVwubCY REwNDL4ZWl3scSXNJc0Tw11KRPMicKLGqlSFrSqt3P4K2oroSf4bbajatFZPNXG5m93H GZN228dYg876d+w5Hli9rQhW8e/A+ehJfCvaUYUHmnWlxopOCK373v9Dn5nOe2LcTZw5 iWDA== X-Gm-Message-State: ACrzQf3XKF8f8Tcqk1vCxLPq9h4WTRK77NCzXa6hNPQeKw1ecKlWy5fg aFQhG6kIvYJrR31/Ys+iPFs= X-Google-Smtp-Source: AMsMyM6tF+5LtuvM3+RsDlAUWhbd1mh1KVjDyH7Gm+2nB/7k8vK5nCGzbQZr8S/RotHecfcfziCx2Q== X-Received: by 2002:a05:600c:6008:b0:3c6:c3fa:c173 with SMTP id az8-20020a05600c600800b003c6c3fac173mr18190298wmb.190.1666466001627; Sat, 22 Oct 2022 12:13:21 -0700 (PDT) Received: from localhost (94.197.1.68.threembb.co.uk. [94.197.1.68]) by smtp.gmail.com with ESMTPSA id i9-20020a5d6309000000b0022afcc11f65sm21846952wru.47.2022.10.22.12.13.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 12:13:21 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/9] ASoC: jz4740-i2s: Handle independent FIFO flush bits Date: Sat, 22 Oct 2022 20:13:00 +0100 Message-Id: <20221022191308.82348-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221022191308.82348-1-aidanmacdonald.0x0@gmail.com> References: <20221022191308.82348-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On the JZ4740, there is a single bit that flushes (empties) both the transmit and receive FIFO. Later SoCs have independent flush bits for each FIFO. Independent FIFOs can be flushed before the snd_soc_dai_active() check because it won't disturb other active streams. This ensures that the FIFO we're about to use is always flushed before starting up. With shared FIFOs we can't do that because if another substream is active, flushing its FIFO would cause underrun errors. This also fixes a bug: since we were only setting the JZ4740's flush bit, which corresponds to the TX FIFO flush bit on other SoCs, other SoCs were not having their RX FIFO flushed at all. Fixes: 967beb2e8777 ("ASoC: jz4740: Add jz4780 support") Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- sound/soc/jz4740/jz4740-i2s.c | 39 ++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index c4c1e89b47c1..83cb81999c6f 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -55,7 +55,8 @@ #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) -#define JZ_AIC_CTRL_FLUSH BIT(8) +#define JZ_AIC_CTRL_TFLUSH BIT(8) +#define JZ_AIC_CTRL_RFLUSH BIT(7) #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) @@ -90,6 +91,8 @@ enum jz47xx_i2s_version { struct i2s_soc_info { enum jz47xx_i2s_version version; struct snd_soc_dai_driver *dai; + + bool shared_fifo_flush; }; struct jz4740_i2s { @@ -116,19 +119,44 @@ static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, writel(value, i2s->base + reg); } +static inline void jz4740_i2s_set_bits(const struct jz4740_i2s *i2s, + unsigned int reg, uint32_t bits) +{ + uint32_t value = jz4740_i2s_read(i2s, reg); + value |= bits; + jz4740_i2s_write(i2s, reg, value); +} + static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf, ctrl; + uint32_t conf; int ret; + /* + * When we can flush FIFOs independently, only flush the FIFO + * that is starting up. We can do this when the DAI is active + * because it does not disturb other active substreams. + */ + if (!i2s->soc_info->shared_fifo_flush) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); + else + jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); + } + if (snd_soc_dai_active(dai)) return 0; - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); - ctrl |= JZ_AIC_CTRL_FLUSH; - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); + /* + * When there is a shared flush bit for both FIFOs, the TFLUSH + * bit flushes both FIFOs. Flushing while the DAI is active would + * cause FIFO underruns in other active substreams so we have to + * guard this behind the snd_soc_dai_active() check. + */ + if (i2s->soc_info->shared_fifo_flush) + jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); ret = clk_prepare_enable(i2s->clk_i2s); if (ret) @@ -443,6 +471,7 @@ static struct snd_soc_dai_driver jz4740_i2s_dai = { static const struct i2s_soc_info jz4740_i2s_soc_info = { .version = JZ_I2S_JZ4740, .dai = &jz4740_i2s_dai, + .shared_fifo_flush = true, }; static const struct i2s_soc_info jz4760_i2s_soc_info = {