From patchwork Sat Mar 4 22:15:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13160026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 129B5C6FD18 for ; Sat, 4 Mar 2023 22:15:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229437AbjCDWPk (ORCPT ); Sat, 4 Mar 2023 17:15:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229519AbjCDWPi (ORCPT ); Sat, 4 Mar 2023 17:15:38 -0500 Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D1B913D4C for ; Sat, 4 Mar 2023 14:15:37 -0800 (PST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 934045C00A3; Sat, 4 Mar 2023 17:15:36 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Sat, 04 Mar 2023 17:15:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1677968136; x= 1678054536; bh=VeDodKZEgELcf7cULKp+pzsVOFJzzBJRdNWzyJCeFOo=; b=L UzeOps1ul0MKFj4NkTI0E0dSg8oaQs3ZVBAGcl4zcSRbAcQTzM/KlKIIMEMNCb38 BjqIbgzffLz+VND+2X/cZYeOGcZXiIE1vGgpCkE6ISIXE/AbE1RoX5JleleptIIs LBc1/IszrpKtPIMWlNVlKq7nxbd12q1NqwmzsWJAEmBAp6S8u7WGsMT5I7Ecp9fI pQjG8KssQfnuIzsZcri9C/Y5JkMcrLuOhdFBQEhwWAM+UBQHVYrEfRsOMG75ICCk e/B0pVRyJUbDDVYq7lL4enMzZ3N8I6qf9E5Vv5BSCLT9rQBMuzbET0AiMvgtdVMU 2d9gKxtKiPcKhs+H39rjQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1677968136; x= 1678054536; bh=VeDodKZEgELcf7cULKp+pzsVOFJzzBJRdNWzyJCeFOo=; b=Z JhfkK50AQLmDdj9rffqltpIObB6xU50yaOlNtG4f1PonKB61dLzfjz6pjpNXLNBZ 4dCKfOsojXhnDEU9Ddt+GLAh29eS2KAHDy03T6TuUr9SoSPbuxZRaSsR8g19nhLS UAhDN6kQwh9xgxkyEH+/I3GdKLCd7+2+/QYqZ6dviksvZ6gZGn9o/0/H3+GRh9qt ewpLZ+TIWoVse7MZ9sbPvQd6xyJsr1d611yV/wZ/KOett1ZHMQT0MlYwH+x2yZUq jIbPBgC9JUPVgjXuja3u/M6DwllqPpa42dEjz3feK2ZG8jhAJA3+245onwMjC6ov gywPu6aldyv1pGRyEOUsA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvddtuddgudehiecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestd ekredtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigr nhhgsehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeevgfdtleegudehge eiudejtdfgtedvudejleevheduhfdvieegtddvvdevffdvhfenucffohhmrghinheptghp shdqvhgvtgdrshgsnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilh hfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhihgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 4 Mar 2023 17:15:35 -0500 (EST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: tsbogend@alpha.franken.de, philmd@linaro.org, Jiaxun Yang Subject: [PATCH 02/12] MIPS: smp-cps: Disable coherence setup for unsupported ISA Date: Sat, 4 Mar 2023 22:15:14 +0000 Message-Id: <20230304221524.47160-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20230304221524.47160-1-jiaxun.yang@flygoat.com> References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org We don't know how to do coherence setup on ISA before MIPS Release 1. As CPS support only servers simulation purpose on those cores, and simulators are always coherent, just disable initialization code and provide user a warning in case coherence is not setup properly. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/cps-vec.S | 5 +++++ arch/mips/kernel/smp-cps.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 8ef492da827f..64ecfdac6580 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -116,6 +116,8 @@ not_nmi: li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS mtc0 t0, CP0_STATUS + /* We don't know how to do coherence setup on earlier ISA */ +#if MIPS_ISA_REV > 0 /* Skip cache & coherence setup if we're already coherent */ lw s7, GCR_CL_COHERENCE_OFS(s1) bnez s7, 1f @@ -129,6 +131,7 @@ not_nmi: li t0, 0xff sw t0, GCR_CL_COHERENCE_OFS(s1) ehb +#endif /* MIPS_ISA_REV > 0 */ /* Set Kseg0 CCA to that in s0 */ 1: mfc0 t0, CP0_CONFIG @@ -515,6 +518,7 @@ LEAF(mips_cps_boot_vpes) nop END(mips_cps_boot_vpes) +#if MIPS_ISA_REV > 0 LEAF(mips_cps_cache_init) /* * Clear the bits used to index the caches. Note that the architecture @@ -588,6 +592,7 @@ dcache_done: jr ra nop END(mips_cps_cache_init) +#endif /* MIPS_ISA_REV > 0 */ #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 4fc288bb85b9..f968a319d87f 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -361,6 +361,8 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) static void cps_init_secondary(void) { + int core = cpu_core(¤t_cpu_data); + /* Disable MT - we only want to run 1 TC per VPE */ if (cpu_has_mipsmt) dmt(); @@ -376,6 +378,9 @@ static void cps_init_secondary(void) BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); } + if (core > 0 && !read_gcr_cl_coherence()) + pr_warn("Core %u is not in coherent domain\n", core); + if (cpu_has_veic) clear_c0_status(ST0_IM); else