@@ -11,29 +11,41 @@
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
+#include <asm/mach-ralink/ralink_regs.h>
#include <asm/time.h>
#include "common.h"
-void ralink_clk_add(const char *dev, unsigned long rate)
+static int clk_cpu_index(void)
{
- struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
+ if (ralink_soc == RALINK_UNKNOWN)
+ return -1;
- if (!clk)
- panic("failed to add clock");
+ if (ralink_soc == MT762X_SOC_MT7620A ||
+ ralink_soc == MT762X_SOC_MT7620N)
+ return 2;
- clkdev_create(clk, NULL, "%s", dev);
+ return 1;
}
void __init plat_time_init(void)
{
+ struct of_phandle_args clkspec;
struct clk *clk;
+ int cpu_clk_idx;
ralink_of_remap();
- ralink_clk_init();
- clk = clk_get_sys("cpu", NULL);
+ cpu_clk_idx = clk_cpu_index();
+ if (cpu_clk_idx == -1)
+ panic("unable to get CPU clock index");
+
+ of_clk_init(NULL);
+ clkspec.np = of_find_node_by_name(NULL, "sysc");
+ clkspec.args_count = 1;
+ clkspec.args[0] = cpu_clk_idx;
+ clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk))
panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
At very early stage on boot, there is a need to set 'mips_hpt_frequency'. This timer frequency is a half of the CPU frequency. To get clocks properly set we need to call to 'of_clk_init()' and properly get cpu clock frequency afterwards. Depending on the SoC, CPU clock index in the clock provider is different being two for MT7620 SoC and one for the rest. Hence, adapt code to be aligned with new clock driver. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> --- arch/mips/ralink/clk.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-)