From patchwork Wed Jun 21 17:49:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 13287817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FE3AEB64D7 for ; Wed, 21 Jun 2023 17:51:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231585AbjFURvg (ORCPT ); Wed, 21 Jun 2023 13:51:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230183AbjFURuk (ORCPT ); Wed, 21 Jun 2023 13:50:40 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31689210B for ; Wed, 21 Jun 2023 10:50:29 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-ba81b37d9d2so6654486276.3 for ; Wed, 21 Jun 2023 10:50:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1687369828; x=1689961828; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=j157PG4NSYE82v2fAItKFhVfRcmmpeiCHUTGpM3SOrs=; b=Gl6wq+mEywBMdam4XfA6Jx3xs02PqlG2630KExwZ+IZ1eaEu2M8C4gqV/l7wcdwgF3 /D1SpZQ0iJjXckKesr45c+8QYgxKeaJkXk4CzLhdqEna8C9zX/I5d6oFGpNmP8iq6sY5 AD2tneZCrgHa95MtCXOU6/zAbzMhBOWLtGo2xx45SVnmLsd1KeV2yL43QUWZzbPYsRE5 0KFNo+sYozd7eoDI93xm/37wexRwY8LUWph38U1kdZ/ZPiRwyt7W5rsyP0dZypbTXy1d v4IZ0o/cb4ZauS58uWHhZOddMD4erO5Pva1AdW/HnuLgUZTI3rDNpeArz5G2OY0RmC2L 7aKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687369828; x=1689961828; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=j157PG4NSYE82v2fAItKFhVfRcmmpeiCHUTGpM3SOrs=; b=MN126v8t5SEicoyvoKUKz9wXFFsgG9eHISG1U3zrb+HZWdnzO0BLIpnEpXeMCDypfZ LQHDEc8T1Hb5R5QSenBzdkAKCCcvbXEr6tNqLXjGvjAQcYVQvJo2uQNAn3Zn0UBCwIh7 dE9QUbxjRnHNKCNv9kQvXyfdopdD0x+JYWcxnHN1aiMdz7S8FY19vWerl8W3rB2g15B5 WIvM+64+rQ1XNhvLPOaEaPNr0eHCjj9pdt/pTY+Zq42NRW74Mb8Sc/FY4PeMR+Q7Pvhp Kar4+2EsC6wx8CpgnMOiEv4TSYZOFm4iQKplMQ9vl4/msiy54hrPhNSAYwpTremMpjEX djzA== X-Gm-Message-State: AC+VfDz8Owvb62xIkQYOq86h8j4slb/XHMOnwCw4GT9kiZeHGCzmULE1 JQVur0yCUIiEgvq4vyeIi+KueJrNI+t+ X-Google-Smtp-Source: ACHHUZ6Ys0yNXltl/QNiOKpOLzit3oOUcal/03jYF6PfCeI/5MRSrcuUGPtaAxFV3KRRmbIadAvYp5jsj7ao X-Received: from rananta-linux.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:22b5]) (user=rananta job=sendgmr) by 2002:a25:74c9:0:b0:ba8:4ff5:3217 with SMTP id p192-20020a2574c9000000b00ba84ff53217mr2202294ybc.3.1687369828056; Wed, 21 Jun 2023 10:50:28 -0700 (PDT) Date: Wed, 21 Jun 2023 17:49:58 +0000 In-Reply-To: <20230621175002.2832640-1-rananta@google.com> Mime-Version: 1.0 References: <20230621175002.2832640-1-rananta@google.com> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog Message-ID: <20230621175002.2832640-8-rananta@google.com> Subject: [RESEND PATCH v5 07/11] KVM: arm64: Define kvm_tlb_flush_vmid_range() From: Raghavendra Rao Ananta To: Oliver Upton , Marc Zyngier , James Morse , Suzuki K Poulose Cc: Paolo Bonzini , Sean Christopherson , Huacai Chen , Zenghui Yu , Anup Patel , Atish Patra , Jing Zhang , Colton Lewis , Raghavendra Rao Anata , David Matlack , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Implement the helper kvm_tlb_flush_vmid_range() that acts as a wrapper for range-based TLB invalidations. For the given VMID, use the range-based TLBI instructions to do the job or fallback to invalidating all the TLB entries. Signed-off-by: Raghavendra Rao Ananta Reviewed-by: Gavin Shan --- arch/arm64/include/asm/kvm_pgtable.h | 10 ++++++++++ arch/arm64/kvm/hyp/pgtable.c | 20 ++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h index 4cd6762bda805..1b12295a83595 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -682,4 +682,14 @@ enum kvm_pgtable_prot kvm_pgtable_stage2_pte_prot(kvm_pte_t pte); * kvm_pgtable_prot format. */ enum kvm_pgtable_prot kvm_pgtable_hyp_pte_prot(kvm_pte_t pte); + +/** + * kvm_tlb_flush_vmid_range() - Invalidate/flush a range of TLB entries + * + * @mmu: Stage-2 KVM MMU struct + * @addr: The base Intermediate physical address from which to invalidate + * @size: Size of the range from the base to invalidate + */ +void kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu, + phys_addr_t addr, size_t size); #endif /* __ARM64_KVM_PGTABLE_H__ */ diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index 3d61bd3e591d2..df8ac14d9d3d4 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -631,6 +631,26 @@ static bool stage2_has_fwb(struct kvm_pgtable *pgt) return !(pgt->flags & KVM_PGTABLE_S2_NOFWB); } +void kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu, + phys_addr_t addr, size_t size) +{ + unsigned long pages, inval_pages; + + if (!system_supports_tlb_range()) { + kvm_call_hyp(__kvm_tlb_flush_vmid, mmu); + return; + } + + pages = size >> PAGE_SHIFT; + while (pages > 0) { + inval_pages = min(pages, MAX_TLBI_RANGE_PAGES); + kvm_call_hyp(__kvm_tlb_flush_vmid_range, mmu, addr, inval_pages); + + addr += inval_pages << PAGE_SHIFT; + pages -= inval_pages; + } +} + #define KVM_S2_MEMATTR(pgt, attr) PAGE_S2_MEMATTR(attr, stage2_has_fwb(pgt)) static int stage2_set_prot_attr(struct kvm_pgtable *pgt, enum kvm_pgtable_prot prot,