From patchwork Wed Nov 29 16:06:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 13473089 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gh9rZSDO" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33863D5E; Wed, 29 Nov 2023 08:15:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701274514; x=1732810514; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NbQPPAhSXc+lH2scgSPRWjHrBuSZh78A/g5NEt950rk=; b=gh9rZSDOer66IGuFShcZ2xoons/WH5cRI3+Vo1ntdjnBMyrvXLBbvj1m zGqEtlVNRDUsOx6A5evhqckcaPC8wVeZEKjrALPKO0b1g3WzwM91rWDvs mzflgBGv3T7Wmz1jUiZlyu2MXNVYZJKX3O7oiwv02c0nIAkATIZfKomsj mZ1ztuuuIP2ZiUxZzUXEgx/R5mj7VXGfy1qsiiMNDxqdpaMmndnao56Pb AOFU4nezbWSEnEfc0Pqnng5ckn6yMkxlUQELbQJTgVYqv9WOSDxvVp8VW QPK+dpJePglzHguTUeAzWE3LeQ/gDgq7pTlkpANwJLm7cGhNUZsdLh6Xk Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="373372529" X-IronPort-AV: E=Sophos;i="6.04,235,1695711600"; d="scan'208";a="373372529" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 08:15:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="892498848" X-IronPort-AV: E=Sophos;i="6.04,235,1695711600"; d="scan'208";a="892498848" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga004.jf.intel.com with ESMTP; 29 Nov 2023 08:15:02 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 5A187A02; Wed, 29 Nov 2023 18:15:01 +0200 (EET) From: Andy Shevchenko To: Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Rasmus Villemoes , =?utf-8?q?Jonathan_Neusch?= =?utf-8?q?=C3=A4fer?= , Krzysztof Kozlowski , =?utf-8?q?Uwe_Kleine-?= =?utf-8?q?K=C3=B6nig?= , Geert Uytterhoeven , Biju Das , Claudiu Beznea , Jianlong Huang , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, openbmc@lists.ozlabs.org, linux-mips@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Ray Jui , Scott Branden , Broadcom internal kernel review list , Dong Aisheng , Fabio Estevam , Shawn Guo , Jacky Bai , Pengutronix Kernel Team , Sascha Hauer , NXP Linux Team , Sean Wang , Paul Cercueil , Lakshmi Sowjanya D , Bjorn Andersson , Andy Gross , Konrad Dybcio , Emil Renner Berthing , Hal Feng Subject: [PATCH v4 04/23] pinctrl: equilibrium: Use temporary variable to hold pins Date: Wed, 29 Nov 2023 18:06:27 +0200 Message-ID: <20231129161459.1002323-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 In-Reply-To: <20231129161459.1002323-1-andriy.shevchenko@linux.intel.com> References: <20231129161459.1002323-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The pins are allocated from the heap, but in order to pass them as constant object, we need to use non-constant pointer. Achieve this by using a temporary variable. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-equilibrium.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c index 54755b583d3f..fd59cfdeefac 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.c +++ b/drivers/pinctrl/pinctrl-equilibrium.c @@ -704,7 +704,7 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata) { struct device *dev = drvdata->dev; struct device_node *node = dev->of_node; - unsigned int *pinmux, pin_id, pinmux_id; + unsigned int *pins, *pinmux, pin_id, pinmux_id; struct group_desc group; struct device_node *np; struct property *prop; @@ -723,15 +723,14 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata) } group.num_pins = err; group.name = prop->value; - group.pins = devm_kcalloc(dev, group.num_pins, - sizeof(*(group.pins)), GFP_KERNEL); - if (!group.pins) { + pins = devm_kcalloc(dev, group.num_pins, sizeof(*pins), GFP_KERNEL); + if (!pins) { of_node_put(np); return -ENOMEM; } + group.pins = pins; - pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux), - GFP_KERNEL); + pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux), GFP_KERNEL); if (!pinmux) { of_node_put(np); return -ENOMEM; @@ -750,7 +749,7 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata) of_node_put(np); return -EINVAL; } - group.pins[j] = pin_id; + pins[j] = pin_id; if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) { dev_err(dev, "Group %s: Read intel pinmux id failed\n", group.name);