| Message ID | 20240113095509.178697-2-huangpei@loongson.cn (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/3] MIPS: adjust exception vector space revervation | expand |
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index b406d8bfb15a..3da35e20d70d 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1992,12 +1992,14 @@ void cpu_probe(void) */ loongson3_cpucfg_synthesize_data(c); + if (cpu == 0) { #ifdef CONFIG_64BIT - if (cpu == 0) __ua_limit = ~((1ull << cpu_vmbits) - 1); #endif + if(!cpu_has_mips_r2_r6) + reserve_exception_space(0, 0x1000); + } - reserve_exception_space(0, 0x1000); } void cpu_report(void)
MIPS R2+ use CP0_Ebase to setup a new exception vector space, instead of using 0x0-0x1000, so it is unnecessary to reserve 0x0-0x1000 for MIPS R2+. If this range is not within valid memoryblock.memory range, memory initialization with CONFIG_DEFERRED_STRUCT_PAGE_INIT failed on 3A1000+(3A1000+ needs other machine-specific fix ) after 61167ad5fecd ("mm: pass nid to reserve_bootmem_region()") Call reserve_exception_space(0,0x1000) only ONCE whether UP or SMP. Signed-off-by: Huang Pei <huangpei@loongson.cn> --- arch/mips/kernel/cpu-probe.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)