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Fri, 2 Feb 2024 13:21:59 -0500 (EST) From: Jiaxun Yang Date: Fri, 02 Feb 2024 18:21:42 +0000 Subject: [PATCH 3/8] MIPS: Fallback CPU -march flag to ISA level if unsupported Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240202-llvm-msym32-v1-3-52f0631057d6@flygoat.com> References: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> In-Reply-To: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> To: Thomas Bogendoerfer , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4062; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=3pIaTRooovaG0E4dcQJ7FyxUskX83he+uJFNra6jZ64=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhtS9Rnts7QrWMnn7PVFYoXRr2sJa8bSnH67+32D1YkavW 8sVldwlHaUsDGJcDLJiiiwhAkp9GxovLrj+IOsPzBxWJpAhDFycAjCRrQcZGe6p/Ph06O5q53+i xofyy1Y5RRxXmLWjqcx36s37uTsbdisx/K9S2mThPvWkWE4e26aHNsbee56klf1I5L3g9jNiWcx jOV4A X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 LLVM does not implement some of -march options. However those options are not mandatory for kernel to build for those CPUs. Fallback -march CFLAG to ISA level if unsupported by toolchain so we can get those kernel to build with LLVM. Link: https://github.com/ClangBuiltLinux/linux/issues/1544 Reported-by: Nathan Chancellor Signed-off-by: Jiaxun Yang --- v0: https://lore.kernel.org/all/20230414080701.15503-7-jiaxun.yang@flygoat.com/ v1: Fix SB1 arch level to mips64 --- arch/mips/Makefile | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index daa569ca4372..91470931a5b8 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -148,10 +148,10 @@ cflags-y += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,) # # CPU-dependent compiler/assembler options for optimization. # -cflags-$(CONFIG_CPU_R3000) += -march=r3000 -cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap -cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap -cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap +cflags-$(CONFIG_CPU_R3000) += $(call cc-option,-march=r3000,-march=mips1) +cflags-$(CONFIG_CPU_R4300) += $(call cc-option,-march=r4300,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_R4X00) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_TX49XX) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg @@ -160,26 +160,30 @@ cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R5) += -march=mips64r5 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap -cflags-$(CONFIG_CPU_P5600) += -march=p5600 -Wa,--trap -modd-spreg -cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap -cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) \ +cflags-$(CONFIG_CPU_P5600) += $(call cc-option,-march=p5600,-march=mips32r5) \ + -Wa,--trap -modd-spreg +cflags-$(CONFIG_CPU_R5000) += $(call cc-option,-march=r5000,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \ +cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \ +cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \ +cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=mips4) \ + -Wa,--trap +cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=mips64) \ -Wa,--trap cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx) cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d) -cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ +cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=mips4) \ -Wa,--trap cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -march=octeon -Wa,--trap cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2E) += \ + $(call cc-option,-march=loongson2e,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2F) += \ + $(call cc-option,-march=loongson2f,-march=mips3) -Wa,--trap # Some -march= flags enable MMI instructions, and GCC complains about that # support being enabled alongside -msoft-float. Thus explicitly disable MMI. cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi)