From patchwork Wed Apr 10 17:12:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13624881 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1F9C1802AD; Wed, 10 Apr 2024 17:12:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712769163; cv=none; b=uGVmUCyLtIBTcL5h3uI3IAlf4erdEIWd9NDfG9KFIZEc1yZePE8UWYsy2Vr/VNPd3XTd4RgAF7EuKKwxI3LXGgEEVSfASDSGFFEAZgbL0tclMO/FhhfPYLWuVc2BD6o/dTaY5LGrSuAPIO6WviNZUtnYFh6NAxOtuqOjXdQ7E8E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712769163; c=relaxed/simple; bh=o9k4BScWsxqBPVgu+3mmJq0aPMvXBAfbm0qYGfu1fLg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IgtJZHy/t10MoMPkYYdEzY8/EKOcLU+yAHJQstI68Kz+NF2NyzxbdeDVqKtysbsEyfSfUS1hRdthiHqkTQxXFjLnbKnP6dB8C2mf4oGFv/QhWRbmR86KFZZ8zneRuDEvK+fZL7AKntA32VNuonnVBOQLIA+ih0Spm2wc4SAmcW0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=R4ND5J3M; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="R4ND5J3M" Received: by mail.gandi.net (Postfix) with ESMTPSA id 6888C1C0007; Wed, 10 Apr 2024 17:12:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712769159; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=66C0T2c7fJuRVzdHb/PD9nAE/qTXLvKb4vCjmWufhEA=; b=R4ND5J3MOocn1Y5Swu1Yjv1jUaZ+5T+3g3r4+q1Q1UyJ33aFztG4l/tgk/kejAS+iVf8Gn c1wY9JLJvbVozMksp5gqBvCe5C4yG8Maum6TTR35tM0xsUS2Nk33K+xLOGjU33L6R8MOHG LoAuvSIJ+ayGZCQ9WMaKVCs+fyMISLjUz+lG4LMv4OYA2IPjW/D7ScJYnc55lCHh/WHuin l3TPUTpaA26JJLqfZjAXLBeUJwUlaPurUbj5wKZrYuYCuDmbdSAOPGPSTU77HJBdtaEuI1 0xZR5y2a9H1kA8xk6bF7d4UZgQYEyAFJu2YVwqhmOXI4NaCfhnZ4iD///A6BRA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 10 Apr 2024 19:12:37 +0200 Subject: [PATCH 08/11] MIPS: mobileye: eyeq5: add OLB syscon node Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240410-mbly-olb-v1-8-335e496d7be3@bootlin.com> References: <20240410-mbly-olb-v1-0-335e496d7be3@bootlin.com> In-Reply-To: <20240410-mbly-olb-v1-0-335e496d7be3@bootlin.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com The OLB ("Other Logic Block") is a syscon region hosting clock, reset and pin controllers. It contains registers such as I2C speed mode that need to be accessible by other nodes. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 6cc5980e2fa1..e82d2a57f6da 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -100,6 +100,14 @@ uart2: serial@a00000 { clock-names = "uartclk", "apb_pclk"; }; + olb: system-controller@e00000 { + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; + reg = <0 0xe00000 0x0 0x400>; + ranges = <0x0 0x0 0xe00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + gic: interrupt-controller@140000 { compatible = "mti,gic"; reg = <0x0 0x140000 0x0 0x20000>;