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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id k8-20020a05600c1c8800b00418a6d62ad0sm9537339wms.34.2024.05.03.06.55.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 06:55:13 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , =?utf-8?q?=C3=81lvaro_Fern=C3=A1n?= =?utf-8?q?dez_Rojas?= , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Daniel_?= =?utf-8?q?Gonz=C3=A1lez_Cabanelas?= Subject: [PATCH 5/6] mips: bmips: enable RAC on BMIPS4350 Date: Fri, 3 May 2024 15:54:05 +0200 Message-ID: <20240503135455.966-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240503135455.966-1-ansuelsmth@gmail.com> References: <20240503135455.966-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel González Cabanelas The data RAC is left disabled by the bootloader in some SoCs, at least in the core it boots from. Enabling this feature increases the performance up to +30% depending on the task. Signed-off-by: Daniel González Cabanelas Signed-off-by: Álvaro Fernández Rojas [ rework code and reduce code duplication ] Signed-off-by: Christian Marangi --- arch/mips/kernel/smp-bmips.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 6048c471b5ee..7bde6bbaa41f 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -617,6 +617,18 @@ void bmips_cpu_setup(void) __raw_readl(bmips_cbr_addr + BMIPS_RAC_ADDRESS_RANGE); break; + case CPU_BMIPS4350: + u32 rac_addr = BMIPS_RAC_CONFIG_1; + + if (!(read_c0_brcm_cmt_local() & (1 << 31))) + rac_addr = BMIPS_RAC_CONFIG; + + /* Enable data RAC */ + cfg = __raw_readl(bmips_cbr_addr + rac_addr); + __raw_writel(cfg | 0xa, bmips_cbr_addr + rac_addr); + __raw_readl(bmips_cbr_addr + rac_addr); + break; + case CPU_BMIPS4380: /* CBG workaround for early BMIPS4380 CPUs */ switch (read_c0_prid()) {