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Sat, 11 May 2024 12:00:26 -0400 (EDT) From: Jiaxun Yang Date: Sat, 11 May 2024 17:00:14 +0100 Subject: [PATCH 7/7] clocksource: mips-gic-timer: Correct sched_clock width Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240511-mips-clks-v1-7-ddb4a10ee9f9@flygoat.com> References: <20240511-mips-clks-v1-0-ddb4a10ee9f9@flygoat.com> In-Reply-To: <20240511-mips-clks-v1-0-ddb4a10ee9f9@flygoat.com> To: Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1957; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=QoFq1d4EB6JF/VXmsnCt30uB7ETZJLm1mA9nrZugG5c=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjT7aZwcr/WclZZ8rzkRMqco7veuiZEM50SNZM7+3Ke6O Vb27ZztHaUsDGIcDLJiiiwhAkp9GxovLrj+IOsPzBxWJpAhDFycAjCRgjSG/95RmfFeJXe+rEgr tmI4y8DhHmYzJ2XChrVmCgxbzZgEvBj+B082ituR2Zid4aYudfrB9EW3unnsmu68CKkL4GPeuSm TCwA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Counter width of GIC is configurable and can be read from a register. Use width value from the register for sched_clock. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé --- drivers/clocksource/mips-gic-timer.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index 67498dc9c5a5..47143e49fc44 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -19,6 +19,7 @@ static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device); static int gic_timer_irq; static unsigned int gic_frequency; +static unsigned int gic_count_width; static bool __read_mostly gic_clock_unstable; static void gic_clocksource_unstable(char *reason); @@ -186,15 +187,14 @@ static void gic_clocksource_unstable(char *reason) static int __init __gic_clocksource_init(void) { - unsigned int count_width; int ret; /* Set clocksource mask. */ - count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; - count_width >>= __ffs(GIC_CONFIG_COUNTBITS); - count_width *= 4; - count_width += 32; - gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); + gic_count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; + gic_count_width >>= __ffs(GIC_CONFIG_COUNTBITS); + gic_count_width *= 4; + gic_count_width += 32; + gic_clocksource.mask = CLOCKSOURCE_MASK(gic_count_width); /* Calculate a somewhat reasonable rating value. */ if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) @@ -264,7 +264,7 @@ static int __init gic_clocksource_of_init(struct device_node *node) if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) { sched_clock_register(mips_cm_is64 ? gic_read_count_64 : gic_read_count_2x32, - 64, gic_frequency); + gic_count_width, gic_frequency); } return 0;