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[v2,1/7] MIPS: csrc-r4k: Refine rating computation

Message ID 20240612-mips-clks-v2-1-a57e6f49f3db@flygoat.com (mailing list archive)
State Accepted
Commit c171186c177970d3ec22dd814f2693f1f7fc1e7d
Headers show
Series MIPS: clocksource cumulative enhancements | expand

Commit Message

Jiaxun Yang June 12, 2024, 8:54 a.m. UTC 
Increase frequency addend dividend to 10000000 (10MHz) to
reasonably accommodate multi GHz level mips_hpt_frequency.

Cap rating of csrc-r4k into 299 to ensure it doesn't go into
"Desired" range, given all the drama we have with CP0 count
registers (SMP sync, behaviour on wait etc).

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v2: Fix up number of zeros for 10 MHz (Maciej)
---
 arch/mips/kernel/csrc-r4k.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
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Patch

diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index edc4afc080fa..f02ae333f4f9 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -111,7 +111,8 @@  int __init init_r4k_clocksource(void)
 		return -ENXIO;
 
 	/* Calculate a somewhat reasonable rating value */
-	clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
+	clocksource_mips.rating = 200;
+	clocksource_mips.rating += clamp(mips_hpt_frequency / 10000000, 0, 99);
 
 	/*
 	 * R2 onwards makes the count accessible to user mode so it can be used