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Wed, 12 Jun 2024 04:54:40 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:33 +0100 Subject: [PATCH v2 6/7] clocksource: mips-gic-timer: Refine rating computation Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240612-mips-clks-v2-6-a57e6f49f3db@flygoat.com> References: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> In-Reply-To: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> To: Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1357; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=ubnQb338iKShZTU1iTrw7BeDTT6ctPCLmk5scTR/g2M=; b=kA0DAAoWQ3EMfdd3KcMByyZiAGZpYkej99mdg8cccBjdsvZE17rDTvcux0h6SSDNZtOc24FAb 4h1BAAWCgAdFiEEVBAijrCB0aDX4Gr8Q3EMfdd3KcMFAmZpYkcACgkQQ3EMfdd3KcMtxwD5Aez6 5355Bn0G0hxyZCy0m/EYO7G5FSQCNetKlyO7ZSUBAM2slUf95REmTxEDq3wILWXN3ShI7x1R8Zc /K3XCOI0M X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 It is a good clocksource which usually go as fast as CPU core and have a low access latency, so raise the base of rating from Good to desired when we know that it has a stable frequency. Increase frequency addend dividend to 10000000 (10MHz) to reasonably accommodate multi GHz level clock, also cap rating within current level. Signed-off-by: Jiaxun Yang --- v2: Fix number of zeros for 10 MHz --- drivers/clocksource/mips-gic-timer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index b3ae38f36720..7a03d94c028a 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -197,7 +197,11 @@ static int __init __gic_clocksource_init(void) gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); /* Calculate a somewhat reasonable rating value. */ - gic_clocksource.rating = 200 + gic_frequency / 10000000; + if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) + gic_clocksource.rating = 300; /* Good when frequecy is stable */ + else + gic_clocksource.rating = 200; + gic_clocksource.rating += clamp(gic_frequency / 10000000, 0, 99); ret = clocksource_register_hz(&gic_clocksource, gic_frequency); if (ret < 0)