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Sat, 10 Aug 2024 08:39:25 -0400 (EDT) From: Jiaxun Yang Date: Sat, 10 Aug 2024 13:39:14 +0100 Subject: [PATCH v3 09/10] irqchip: irq-mips-cpu: Rework software IRQ handling flow Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240810-b4-mips-ipi-improvements-v3-9-1224fd7c4096@flygoat.com> References: <20240810-b4-mips-ipi-improvements-v3-0-1224fd7c4096@flygoat.com> In-Reply-To: <20240810-b4-mips-ipi-improvements-v3-0-1224fd7c4096@flygoat.com> To: Thomas Bogendoerfer , Florian Fainelli , Broadcom internal kernel review list , Huacai Chen , Thomas Gleixner , Serge Semin , Paul Burton Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3817; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=QtTWy2Q+e5XNNE3vkRpp+K1MfQ6P5KmM8+2jFpqTlyI=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTt8fnR1XuZz/zmn6LvMTfy4Az7As6F26wlUwuVjKzXL Zy4JEG5o5SFQYyLQVZMkSVEQKlvQ+PFBdcfZP2BmcPKBDKEgYtTACbioM/I8I5FmJ957XnLGbLf a74Yf1x2iKPJyFWlMXaKksKHF9N/HmFkWDv9/6LtHhUzFLnbZn2dsFBAzYj1lOXC308/7I1aaD6 tlgsA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Remove unnecessary irq_chip hooks for software interrupts, and don't mask them in ack hook to match kernel's expectation on handling flow. Create a irq_chip for regular (non-MT) mode software interrupts so they will be acked as well. Tested-by: Serge Semin Signed-off-by: Jiaxun Yang --- drivers/irqchip/irq-mips-cpu.c | 57 +++++++++++++++++++++++++++++------------- 1 file changed, 39 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index 7b3501485d95..4854c06ce652 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -49,7 +49,21 @@ static inline void mask_mips_irq(struct irq_data *d) irq_disable_hazard(); } -static struct irq_chip mips_cpu_irq_controller = { +static unsigned int mips_sw_irq_startup(struct irq_data *d) +{ + clear_c0_cause(C_SW0 << d->hwirq); + back_to_back_c0_hazard(); + unmask_mips_irq(d); + return 0; +} + +static void mips_sw_irq_ack(struct irq_data *d) +{ + clear_c0_cause(C_SW0 << d->hwirq); + back_to_back_c0_hazard(); +} + +static const struct irq_chip mips_cpu_irq_controller = { .name = "MIPS", .irq_ack = mask_mips_irq, .irq_mask = mask_mips_irq, @@ -60,11 +74,19 @@ static struct irq_chip mips_cpu_irq_controller = { .irq_enable = unmask_mips_irq, }; +static const struct irq_chip mips_cpu_sw_irq_controller = { + .name = "MIPS", + .irq_startup = mips_sw_irq_startup, + .irq_ack = mips_sw_irq_ack, + .irq_mask = mask_mips_irq, + .irq_unmask = unmask_mips_irq, +}; + +#ifdef CONFIG_MIPS_MT /* * Basically the same as above but taking care of all the MT stuff */ - -static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) +static unsigned int mips_mt_sw_irq_startup(struct irq_data *d) { unsigned int vpflags = dvpe(); @@ -76,14 +98,14 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) /* * While we ack the interrupt interrupts are disabled and thus we don't need - * to deal with concurrency issues. Same for mips_cpu_irq_end. + * to deal with concurrency issues. */ -static void mips_mt_cpu_irq_ack(struct irq_data *d) +static void mips_mt_sw_irq_ack(struct irq_data *d) { unsigned int vpflags = dvpe(); + clear_c0_cause(C_SW0 << d->hwirq); evpe(vpflags); - mask_mips_irq(d); } #ifdef CONFIG_GENERIC_IRQ_IPI @@ -108,21 +130,17 @@ static void mips_mt_send_ipi(struct irq_data *d, unsigned int cpu) } #endif /* CONFIG_GENERIC_IRQ_IPI */ - -static struct irq_chip mips_mt_cpu_irq_controller = { +static const struct irq_chip mips_mt_cpu_irq_controller = { .name = "MIPS", - .irq_startup = mips_mt_cpu_irq_startup, - .irq_ack = mips_mt_cpu_irq_ack, + .irq_startup = mips_mt_sw_irq_startup, + .irq_ack = mips_mt_sw_irq_ack, .irq_mask = mask_mips_irq, - .irq_mask_ack = mips_mt_cpu_irq_ack, .irq_unmask = unmask_mips_irq, - .irq_eoi = unmask_mips_irq, - .irq_disable = mask_mips_irq, - .irq_enable = unmask_mips_irq, #ifdef CONFIG_GENERIC_IRQ_IPI .ipi_send_single = mips_mt_send_ipi, #endif }; +#endif asmlinkage void __weak plat_irq_dispatch(void) { @@ -152,11 +170,14 @@ asmlinkage void __weak plat_irq_dispatch(void) static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { - struct irq_chip *chip; + const struct irq_chip *chip; - if (hw < 2 && cpu_has_mipsmt) { - /* Software interrupts are used for MT/CMT IPI */ - chip = &mips_mt_cpu_irq_controller; + if (hw < 2) { + chip = &mips_cpu_sw_irq_controller; +#ifdef CONFIG_MIPS_MT + if (cpu_has_mipsmt) + chip = &mips_mt_cpu_irq_controller; +#endif } else { chip = &mips_cpu_irq_controller; }