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AJvYcCWJblsRhrxTdlX79dgXV3FufA4dgwg6OPHkMxVUXEWl/Vg92RMYwioHmuRU2XGIBZfoTRIXJy7zVdWQoqs=@vger.kernel.org, AJvYcCX3I4DdVLKoRbyT9sysOFGQI0q7tYMGatqpFl18JrtU+5Gm+V/d3Lg/CdXauiW6PD7nUZUoUtLvwFuzJw==@vger.kernel.org X-Gm-Message-State: AOJu0YzLXLMIInusqhWowvgEfqFxHKeuvJxnRbuKzU29lGLRswcKtUGp LQIgDuPbHrCzwq0yVUXRO0ny1MKBgDYo5GeCmtvwzSpPxVCA4xut X-Google-Smtp-Source: AGHT+IEybtMSJJTB1GlywNRQRpKklzRj1/3/mMkf52VBoXC32u7TNHFjKT71CJaNokZhu8eUiNJDKA== X-Received: by 2002:a17:907:7211:b0:a99:55ab:b666 with SMTP id a640c23a62f3a-a9a69a80a16mr479865566b.34.1729321862735; Sat, 19 Oct 2024 00:11:02 -0700 (PDT) Received: from localhost.localdomain ([79.175.114.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a68c27841sm180566666b.192.2024.10.19.00.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 00:11:02 -0700 (PDT) From: Aleksandar Rikalo To: Thomas Bogendoerfer Cc: Aleksandar Rikalo , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Thomas Gleixner , Tiezhu Yang , Gregory CLEMENT Subject: [PATCH v7 10/12] dt-bindings: mips: cpu: Add property for broken HCI information Date: Sat, 19 Oct 2024 09:10:35 +0200 Message-Id: <20241019071037.145314-11-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241019071037.145314-1-arikalo@gmail.com> References: <20241019071037.145314-1-arikalo@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Gregory CLEMENT Some CM3.5 reports show that Hardware Cache Initialization is complete, but in reality it's not the case. They also incorrectly indicate that Hardware Cache Initialization is supported. This optional property allows warning about this broken feature that cannot be detected at runtime. Signed-off-by: Gregory CLEMENT Signed-off-by: Aleksandar Rikalo --- Documentation/devicetree/bindings/mips/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index a85137add668..57e93c07ab1b 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -47,6 +47,12 @@ properties: clocks: maxItems: 1 + cm3-l2-config-hci-broken: + type: boolean + description: + If present, indicates that the HCI (Hardware Cache Initialization) + information for the L2 cache in multi-cluster configuration is broken. + device_type: true allOf: