From patchwork Wed Mar 5 11:05:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keguang Zhang via B4 Relay X-Patchwork-Id: 14002457 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 678D31A2397; Wed, 5 Mar 2025 11:05:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741172712; cv=none; b=PDUuxiBC/lQXWmq7jHuuGg5ht37M+EzmgrXMQsyGnVH5qQN8Lw0L5d5Ixk9+vO1QSHR5L5vuJoeyJTLnvdyp8h1Kn83Zn08JVFWuj8agCaUMSKBi7v/jWTn2/cTSrxln3IqUC+zZxVS/vfe5lrWl+LJXqSaKHRxS1GEACP7cllo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741172712; c=relaxed/simple; bh=Wn+HkeuykAgkMxuLx9Wzsoz+97Luiz91NvrSXcwMjaw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=C/Tkh9WHCGmQhgZ55+pYB3yTmwq902YYitd2EY+VsgjBQqGWLxJmyfSO4ZZnKdtoasmnZeT6+3mhZGUHbVgyR3DUiuRuXe/2nR5tm0C1Ll3IZmXAwT3J+Ci2lWtNkyCrv224/E1Yh/woZpOhG8mi7Hbs5mvHGmPi5+udDiG0hW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qBVkWa+T; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qBVkWa+T" Received: by smtp.kernel.org (Postfix) with ESMTPS id E63F0C4CEE9; Wed, 5 Mar 2025 11:05:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741172712; bh=Wn+HkeuykAgkMxuLx9Wzsoz+97Luiz91NvrSXcwMjaw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qBVkWa+TLzXxlfX4DDUSH4nq9ONz+wRBPrDRFEtsnC1JtdrbntnlD4+5zDdn+TpNf 8XdkHi05I4IgJkNEj6GiNjPFidGSTd5Sq3z3rihU24JnouQmUBxJWaGjrh14fGzQf1 J5GnDnUEe2TPnshIO2fIE80llYIBnpnNjRHFHNMX0MZyqtqQbYInzCiM3PTNwIKRI0 RyU/qkoI0All4z17Lk6T6bagQKh8e3BpQHquXg4kIfiQYhNimWOAgjr5PhMqDdolzF VQelBSkQOIxgER1EqNwnCoAxifC79sK0v1FFlFVxuznTP4KXexU6MfYcBNM4ig51pq vuZE5MlthWNmw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4081C19F32; Wed, 5 Mar 2025 11:05:11 +0000 (UTC) From: Keguang Zhang via B4 Relay Date: Wed, 05 Mar 2025 19:05:04 +0800 Subject: [PATCH v13 1/2] dt-bindings: mtd: Add Loongson-1 NAND Controller Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-loongson1-nand-v13-1-a5bac21631cd@gmail.com> References: <20250305-loongson1-nand-v13-0-a5bac21631cd@gmail.com> In-Reply-To: <20250305-loongson1-nand-v13-0-a5bac21631cd@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, Keguang Zhang , Krzysztof Kozlowski X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1741172709; l=3113; i=keguang.zhang@gmail.com; s=20231129; h=from:subject:message-id; bh=EoSyInd/tPhcSSV/G9oyENpJ97B1jinURWqxESSsYu4=; b=nlQ8VE3UGDfj1uy6AWCHyUafsaGiIs4oXzhdyhTBrg+wQYX2jV1K0eIlDZPkAWQkMLHQxDUHk W+LvJ9mUJBCDEXmySc3RVeyMrLqbFeE2DkCNJ0D++RyyXAFYMPBjTAp X-Developer-Key: i=keguang.zhang@gmail.com; a=ed25519; pk=FMKGj/JgKll/MgClpNZ3frIIogsh5e5r8CeW2mr+WLs= X-Endpoint-Received: by B4 Relay for keguang.zhang@gmail.com/20231129 with auth_id=102 X-Original-From: Keguang Zhang Reply-To: keguang.zhang@gmail.com From: Keguang Zhang Add devicetree binding document for Loongson-1 NAND controller. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Keguang Zhang --- Changes in v13: - None Changes in v12: - Add MTD label in the example. Changes in v11: - Remove the requirement for 'nand-use-soft-ecc-engine' and 'nand-ecc-algo'. - Add 'reg-names' to support DMA address. Changes in v10: - None Changes in v9: - Change the compatible to 'loongson,ls1*-nand-controller'. - Rename the file to loongson,ls1b-nand-controller.yaml - Some minor adjustments. Changes in v8: - Add a description part. - Adjust the compatible because the match data for ls1c-nfc differs from ls1b-nfc. - Mark 'nand-use-soft-ecc-engine' and 'nand-ecc-algo' as mandatory. - Delete the superfluous blank lines. Changes in v7: - rename the file to loongson,ls1b-nfc.yaml Changes in v6: - A newly added patch --- .../mtd/loongson,ls1b-nand-controller.yaml | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml b/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml new file mode 100644 index 000000000000..a09e92e416c4 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/loongson,ls1b-nand-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-1 NAND Controller + +maintainers: + - Keguang Zhang + +description: + The Loongson-1 NAND controller abstracts all supported operations, + meaning it does not support low-level access to raw NAND flash chips. + Moreover, the controller is paired with the DMA engine to perform + READ and PROGRAM functions. + +allOf: + - $ref: nand-controller.yaml + +properties: + compatible: + oneOf: + - enum: + - loongson,ls1b-nand-controller + - loongson,ls1c-nand-controller + - items: + - enum: + - loongson,ls1a-nand-controller + - const: loongson,ls1b-nand-controller + + reg: + maxItems: 2 + + reg-names: + items: + - const: nand + - const: nand-dma + + dmas: + maxItems: 1 + + dma-names: + const: rxtx + +required: + - compatible + - reg + - reg-names + - dmas + - dma-names + +unevaluatedProperties: false + +examples: + - | + nand-controller@1fe78000 { + compatible = "loongson,ls1b-nand-controller"; + reg = <0x1fe78000 0x24>, <0x1fe78040 0x4>; + reg-names = "nand", "nand-dma"; + dmas = <&dma 0>; + dma-names = "rxtx"; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + label = "ls1x-nand"; + nand-use-soft-ecc-engine; + nand-ecc-algo = "hamming"; + }; + };