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Fri, 27 Jul 2018 19:10:17 +0000 From: Petr Machata To: Subject: [PATCH net-next mlxsw v3 04/10] mlxsw: reg: Add QoS Priority Trust State Register In-Reply-To: References: Message-Id: <24a944b1d11131d353b4a498cac7418283a9f4c1.1532716714.git.petrm@mellanox.com> Date: Fri, 27 Jul 2018 21:10:06 +0200 User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 X-Originating-IP: [78.45.160.211] X-ClientProxiedBy: VI1PR08CA0119.eurprd08.prod.outlook.com (2603:10a6:800:d4::21) To AM6PR05MB4184.eurprd05.prod.outlook.com (2603:10a6:209:40::29) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 14daf3b2-65ff-4797-5be1-08d5f3f49720 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989117)(5600074)(711020)(4618075)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(2017052603328)(7153060)(7193020); SRVR:AM6PR05MB4184; X-Microsoft-Exchange-Diagnostics: 1; AM6PR05MB4184; 3:cll5GZQ6aPDYhFaHkLxSIaw8MIthndrYhJ11f87PmY9ERUpilKxAX553rTxhtwNFTKBNkfqLaUI1uaj4Ik9eP2MPOXHiR9TtoBrzJlgrRNWSU0P0fwefprZGnTCUryBU6vjWx57puCnJUtWrTUEaSSqNkPn/BBxP80Tm02X8rxOl7EzBffLj3oKKM2Px7JQAuKsbtCQpUgRBolgDBxXRwNyEsNSjscO3lsGqaD5CtrfNF4ptabj85YjS7/oeQoGY; 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Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 39 +++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 411d06b5aaae..c50e754dd725 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -3017,6 +3017,44 @@ static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); } +/* QPTS - QoS Priority Trust State Register + * ---------------------------------------- + * This register controls the port policy to calculate the switch priority and + * packet color based on incoming packet fields. + */ +#define MLXSW_REG_QPTS_ID 0x4002 +#define MLXSW_REG_QPTS_LEN 0x8 + +MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); + +/* reg_qpts_local_port + * Local port number. + * Access: Index + * + * Note: CPU port is supported. + */ +MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); + +enum mlxsw_reg_qpts_trust_state { + MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, + MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ +}; + +/* reg_qpts_trust_state + * Trust state for a given port. + * Access: RW + */ +MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); + +static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, + enum mlxsw_reg_qpts_trust_state ts) +{ + MLXSW_REG_ZERO(qpts, payload); + + mlxsw_reg_qpts_local_port_set(payload, local_port); + mlxsw_reg_qpts_trust_state_set(payload, ts); +} + /* QPCR - QoS Policer Configuration Register * ----------------------------------------- * The QPCR register is used to create policers - that limit @@ -8590,6 +8628,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { MLXSW_REG(percr), MLXSW_REG(pererp), MLXSW_REG(iedr), + MLXSW_REG(qpts), MLXSW_REG(qpcr), MLXSW_REG(qtct), MLXSW_REG(qeec),