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Fri, 27 Jul 2018 19:10:22 +0000 From: Petr Machata To: Subject: [PATCH net-next mlxsw v3 05/10] mlxsw: reg: Add QoS ReWrite Enable Register In-Reply-To: References: Message-Id: <9d4fe1d3061619846b4942d1a2083f97c9a5e602.1532716714.git.petrm@mellanox.com> Date: Fri, 27 Jul 2018 21:10:18 +0200 User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 X-Originating-IP: [78.45.160.211] X-ClientProxiedBy: AM0PR01CA0010.eurprd01.prod.exchangelabs.com (2603:10a6:208:69::23) To AM0PR05MB4178.eurprd05.prod.outlook.com (2603:10a6:208:57::27) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5f4ff4ca-fcb0-4996-f6a4-08d5f3f49a45 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989117)(5600074)(711020)(4618075)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(2017052603328)(7153060)(7193020); SRVR:AM0PR05MB4178; X-Microsoft-Exchange-Diagnostics: 1; AM0PR05MB4178; 3:3zDtoRFfjmBUnduCvv/Iey+Zr8PUGst+q8sA2n7oSzNsBnBkN18p3ZseSCA+loASmR0ubDI5cLZiJ64/gS6u9j4eOx+kWdorijiyeWky8AQ+66BFXBv1Da52ftwjNELM+NoWXN29UrsAZ1saO5tgWZ3PV2nfyOqsazCxwazMna+ThmnuLalE/is7B0vdRTFxA2c8va2o7WV7oQ5TSL9o8+kRnT7TWChYBeGHYa2ZuzisnOMVkIU2mNPowDPxy7iY; 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Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 39 +++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index c50e754dd725..02c0e1531ed2 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -3367,6 +3367,44 @@ static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, mlxsw_reg_qeec_next_element_index_set(payload, next_index); } +/* QRWE - QoS ReWrite Enable + * ------------------------- + * This register configures the rewrite enable per receive port. + */ +#define MLXSW_REG_QRWE_ID 0x400F +#define MLXSW_REG_QRWE_LEN 0x08 + +MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); + +/* reg_qrwe_local_port + * Local port number. + * Access: Index + * + * Note: CPU port is supported. No support for router port. + */ +MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); + +/* reg_qrwe_dscp + * Whether to enable DSCP rewrite (default is 0, don't rewrite). + * Access: RW + */ +MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); + +/* reg_qrwe_pcp + * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). + * Access: RW + */ +MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); + +static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, + bool rewrite_pcp, bool rewrite_dscp) +{ + MLXSW_REG_ZERO(qrwe, payload); + mlxsw_reg_qrwe_local_port_set(payload, local_port); + mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); + mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); +} + /* QPDPM - QoS Port DSCP to Priority Mapping Register * -------------------------------------------------- * This register controls the mapping from DSCP field to @@ -8632,6 +8670,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { MLXSW_REG(qpcr), MLXSW_REG(qtct), MLXSW_REG(qeec), + MLXSW_REG(qrwe), MLXSW_REG(qpdpm), MLXSW_REG(pmlp), MLXSW_REG(pmtu),