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Wed, 25 Jul 2018 13:53:46 +0000 From: Petr Machata To: Subject: [PATCH net-next mlxsw v2 5/8] mlxsw: reg: Add QoS ReWrite Enable Register In-Reply-To: References: Message-Id: Date: Wed, 25 Jul 2018 15:53:42 +0200 User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 X-Originating-IP: [78.45.160.211] X-ClientProxiedBy: VI1P189CA0031.EURP189.PROD.OUTLOOK.COM (2603:10a6:802:2a::44) To DB7PR05MB4188.eurprd05.prod.outlook.com (2603:10a6:5:18::29) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 80253d73-f433-466e-74f4-08d5f2360af5 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989117)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600073)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:DB7PR05MB4188; X-Microsoft-Exchange-Diagnostics: 1; DB7PR05MB4188; 3:JBewTCgB93a2k0cvBDZptRwua+o16YwmzB+QHcOOvckgERHYUTMIzFFg/crt3jPlWvPUabbR9waBY1UtpUMST0AAWDsxcsXux7Q2WWlOKHoQ6q+kSsa2wPNwbeubdS9yByixKIxddaqxgy5Md5TBSVwFdXHJdtvKggcO4fWAXsAH1qPjLV+ver1KDkuy0cjfTGBV7ZVPmsZd6BzSFZI5r4GlpOjz9fPHe/tSxO6KdG87nxF6gsPgApFdA1WqdW3L; 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Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 39 +++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index efc989e7c842..14e75b8afcfa 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -3082,6 +3082,44 @@ static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, mlxsw_reg_qeec_next_element_index_set(payload, next_index); } +/* QRWE - QoS ReWrite Enable + * ------------------------- + * This register configures the rewrite enable per receive port. + */ +#define MLXSW_REG_QRWE_ID 0x400F +#define MLXSW_REG_QRWE_LEN 0x08 + +MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); + +/* reg_qrwe_local_port + * Local port number. + * Access: Index + * + * Note: CPU port is supported. No support for router port. + */ +MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); + +/* reg_qrwe_dscp + * Whether to enable DSCP rewrite (default is 0, don't rewrite). + * Access: RW + */ +MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); + +/* reg_qrwe_pcp + * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). + * Access: RW + */ +MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); + +static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, + bool rewrite_pcp, bool rewrite_dscp) +{ + MLXSW_REG_ZERO(qrwe, payload); + mlxsw_reg_qrwe_local_port_set(payload, local_port); + mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); + mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); +} + /* QPDPM - QoS Port DSCP to Priority Mapping Register * -------------------------------------------------- * This register controls the mapping from DSCP field to @@ -8345,6 +8383,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { MLXSW_REG(qpcr), MLXSW_REG(qtct), MLXSW_REG(qeec), + MLXSW_REG(qrwe), MLXSW_REG(qpdpm), MLXSW_REG(pmlp), MLXSW_REG(pmtu),