From patchwork Tue May 19 17:54:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 11558277 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09726138A for ; Tue, 19 May 2020 18:01:45 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id CC43120826 for ; Tue, 19 May 2020 18:01:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="M9vyZZ9m" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CC43120826 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 007FC80007; Tue, 19 May 2020 14:01:44 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id EFB4C900002; Tue, 19 May 2020 14:01:43 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id DC31480007; Tue, 19 May 2020 14:01:43 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0122.hostedemail.com [216.40.44.122]) by kanga.kvack.org (Postfix) with ESMTP id C1F77900002 for ; Tue, 19 May 2020 14:01:43 -0400 (EDT) Received: from smtpin14.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay04.hostedemail.com (Postfix) with ESMTP id 7D6B2585D for ; Tue, 19 May 2020 18:01:43 +0000 (UTC) X-FDA: 76834236486.14.mom19_2c1df6764fd12 X-Spam-Summary: 10,1,0,7062b673e84e7de0,d41d8cd98f00b204,jean-philippe@linaro.org,,RULES_HIT:41:334:355:368:369:379:541:800:966:967:968:973:988:989:1260:1311:1314:1345:1437:1515:1535:1543:1711:1730:1747:1777:1792:1801:2196:2199:2376:2393:2525:2559:2563:2682:2685:2859:2895:2933:2937:2939:2942:2945:2947:2951:2954:3022:3138:3139:3140:3141:3142:3354:3865:3867:3868:3870:3871:3874:3934:3936:3938:3941:3944:3947:3950:3953:3956:3959:4117:4250:4321:4385:4605:5007:6119:6261:6653:6742:7903:9010:9025:9509:10004:11026:11658:11914:12043:12048:12296:12297:12438:12517:12519:12555:12663:12679:12895:12986:13138:13161:13229:13231:13894:13972:14096:14181:14394:14721:21080:21213:21220:21222:21433:21444:21451:21611:21627:21749:21811:21891:30012:30054:30055:30070:30089,0,RBL:209.85.221.67:@linaro.org:.lbl8.mailshell.net-62.14.0.100 66.201.201.201,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:ft,MSBL:0,DNSBL:neutral,Custom_rules:0:0:0,LFtime:26,LUA_SUMMARY:none X-HE-Tag: mom19_2c1df6764fd12 X-Filterd-Recvd-Size: 6877 Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by imf44.hostedemail.com (Postfix) with ESMTP for ; Tue, 19 May 2020 18:01:43 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id s8so379050wrt.9 for ; Tue, 19 May 2020 11:01:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=bX55m437g7MeykE1US3Tftk0H5lzLx6XUpXZp2Kvxoc=; b=M9vyZZ9mATtJfZDUOxfdmdgx0RZHnvTGKbSm5F+JwH4itQZSpjYwKXYMCkR2huFvi2 twh626xwy7oiPNTooN5mL8olWtFlkxdKNWun/7JJy52nt9PxCNGgU3iNKo7o3OgGBjBv GtcGwtOW+y4rz0r0Z0/zqBdnL/m4CdO70VTsExVbCbEatxP0xilLLUZJnBsBvKMv2tyJ vq/V4yM3GGmE/FtHGK5VR9w0BMSpmTebXfbAaoplg6/qbzV58lFR5DsR+sAVolk1TARd 9BUbrrk/lyNFvpD6HXmUxfASJGR586E46CfIK9SG/6YNZ8RwjVHLC9QEQCyMTEN7B8Bf 1ctA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=bX55m437g7MeykE1US3Tftk0H5lzLx6XUpXZp2Kvxoc=; b=GyLHFO08jsxP2JxVFnbaBHh1rLa4sZmQtaw1R/UV8WHSX9+IXAsj4ZoBLDCIzZ/i9c ZUjcyNU23XHCwWzK/kKrg9xGk+J/qcgBRdE1jTTfGpL7yWrszlCLAJxo4XZdLMK6CYS4 BmKtVPHFQl/BVzzMjV1vD9MrxOXJ0gdO6A4IwFp1CLQotEsLmuL2eManKf9wEj/ygXn0 M1PtsWEi4up9ArV9vDi7r+2tHT71l2bbSzJqneW5q5ICN8m39YcY5EmWiDQQB0nHQrdI bxxtvlyekpGSvZJlg6AqYcj/n0kJsfMJThxeKZbYfekdYwxo8S2IcR7Rr31rTSssurG9 EVdw== X-Gm-Message-State: AOAM532wXImW3V87/+5Gh4FZLvXxF3U9cZKTA3myxv/yCdKnhSImnUgI cyzscrrkpvNVv7BsniylQRyFjw== X-Google-Smtp-Source: ABdhPJx1fsDPOtceAXONrGmaumNlQajybGcyP41uWlcXsFpwhVtjyrg3sPruM6jEsNsAR5hEmsZ2Cw== X-Received: by 2002:adf:ec88:: with SMTP id z8mr125600wrn.44.1589911301763; Tue, 19 May 2020 11:01:41 -0700 (PDT) Received: from localhost.localdomain ([2001:171b:226e:c200:c43b:ef78:d083:b355]) by smtp.gmail.com with ESMTPSA id 1sm510496wmz.13.2020.05.19.11.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2020 11:01:41 -0700 (PDT) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-mm@kvack.org Cc: joro@8bytes.org, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, kevin.tian@intel.com, baolu.lu@linux.intel.com, Jonathan.Cameron@huawei.com, jacob.jun.pan@linux.intel.com, christian.koenig@amd.com, felix.kuehling@amd.com, zhangfei.gao@linaro.org, jgg@ziepe.ca, xuzaibo@huawei.com, fenghua.yu@intel.com, hch@infradead.org, Jean-Philippe Brucker Subject: [PATCH v7 00/24] iommu: Shared Virtual Addressing for SMMUv3 Date: Tue, 19 May 2020 19:54:38 +0200 Message-Id: <20200519175502.2504091-1-jean-philippe@linaro.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Shared Virtual Addressing (SVA) allows to share process page tables with devices using the IOMMU, PASIDs and I/O page faults. Add SVA support to the Arm SMMUv3 driver. Since v6 [1]: * Rename ioasid_free() to ioasid_put() in patch 02, requiring changes to the Intel drivers. * Use mmu_notifier_register() in patch 16 to avoid copying the ops and simplify the invalidate() notifier in patch 17. * As a result, replace context spinlock with a mutex. Simplified locking in patch 11 (That patch still looks awful, but I think the series is more readable overall). And I've finally been able to remove the GFP_ATOMIC allocations. * Use a single patch (04) for io-pgfault.c, since the code was simplified in v6. Fixed partial list in patch 04. [1] https://lore.kernel.org/linux-iommu/20200430143424.2787566-1-jean-philippe@linaro.org/ Jean-Philippe Brucker (24): mm: Add a PASID field to mm_struct iommu/ioasid: Add ioasid references iommu/sva: Add PASID helpers iommu: Add a page fault handler arm64: mm: Add asid_gen_match() helper arm64: mm: Pin down ASIDs for sharing mm with devices iommu/io-pgtable-arm: Move some definitions to a header iommu/arm-smmu-v3: Manage ASIDs with xarray arm64: cpufeature: Export symbol read_sanitised_ftr_reg() iommu/arm-smmu-v3: Share process page tables iommu/arm-smmu-v3: Seize private ASID iommu/arm-smmu-v3: Add support for VHE iommu/arm-smmu-v3: Enable broadcast TLB maintenance iommu/arm-smmu-v3: Add SVA feature checking iommu/arm-smmu-v3: Add SVA device feature iommu/arm-smmu-v3: Implement iommu_sva_bind/unbind() iommu/arm-smmu-v3: Hook up ATC invalidation to mm ops iommu/arm-smmu-v3: Add support for Hardware Translation Table Update iommu/arm-smmu-v3: Maintain a SID->device structure dt-bindings: document stall property for IOMMU masters iommu/arm-smmu-v3: Add stall support for platform devices PCI/ATS: Add PRI stubs PCI/ATS: Export PRI functions iommu/arm-smmu-v3: Add support for PRI drivers/iommu/Kconfig | 12 + drivers/iommu/Makefile | 2 + .../devicetree/bindings/iommu/iommu.txt | 18 + arch/arm64/include/asm/mmu.h | 1 + arch/arm64/include/asm/mmu_context.h | 11 +- drivers/iommu/io-pgtable-arm.h | 30 + drivers/iommu/iommu-sva.h | 15 + include/linux/ioasid.h | 10 +- include/linux/iommu.h | 53 + include/linux/mm_types.h | 4 + include/linux/pci-ats.h | 8 + arch/arm64/kernel/cpufeature.c | 1 + arch/arm64/mm/context.c | 103 +- drivers/iommu/arm-smmu-v3.c | 1552 +++++++++++++++-- drivers/iommu/intel-iommu.c | 4 +- drivers/iommu/intel-svm.c | 6 +- drivers/iommu/io-pgfault.c | 459 +++++ drivers/iommu/io-pgtable-arm.c | 27 +- drivers/iommu/ioasid.c | 38 +- drivers/iommu/iommu-sva.c | 85 + drivers/iommu/of_iommu.c | 5 +- drivers/pci/ats.c | 4 + MAINTAINERS | 3 +- 23 files changed, 2286 insertions(+), 165 deletions(-) create mode 100644 drivers/iommu/io-pgtable-arm.h create mode 100644 drivers/iommu/iommu-sva.h create mode 100644 drivers/iommu/io-pgfault.c create mode 100644 drivers/iommu/iommu-sva.c