mbox series

[RFC,-V3,0/5] autonuma: Optimize memory placement for memory tiering system

Message ID 20200825002354.17038-1-ying.huang@intel.com (mailing list archive)
Headers show
Series autonuma: Optimize memory placement for memory tiering system | expand

Message

Huang, Ying Aug. 25, 2020, 12:23 a.m. UTC 
With the advent of various new memory types, some machines will have
multiple types of memory, e.g. DRAM and PMEM (persistent memory).  The
memory subsystem of these machines can be called memory tiering
system, because the performance of the different types of memory are
usually different.

After commit c221c0b0308f ("device-dax: "Hotplug" persistent memory
for use like normal RAM"), the PMEM could be used as the
cost-effective volatile memory in separate NUMA nodes.  In a typical
memory tiering system, there are CPUs, DRAM and PMEM in each physical
NUMA node.  The CPUs and the DRAM will be put in one logical node,
while the PMEM will be put in another (faked) logical node.

To optimize the system overall performance, the hot pages should be
placed in DRAM node.  To do that, we need to identify the hot pages in
the PMEM node and migrate them to DRAM node via NUMA migration.

In the original AutoNUMA, there are already a set of existing
mechanisms to identify the pages recently accessed by the CPUs in a
node and migrate the pages to the node.  So we can reuse these
mechanisms to build the mechanisms to optimize the page placement in
the memory tiering system.  This has been implemented in this
patchset.

At the other hand, the cold pages should be placed in PMEM node.  So,
we also need to identify the cold pages in the DRAM node and migrate
them to PMEM node.

In the following patchset,

[RFC][PATCH 0/9] [v3] Migrate Pages in lieu of discard
https://lkml.kernel.org/lkml/20200818184122.29C415DF@viggo.jf.intel.com/

A mechanism to demote the cold DRAM pages to PMEM node under memory
pressure is implemented.  Based on that, the cold DRAM pages can be
demoted to PMEM node proactively to free some memory space on DRAM
node.  And this frees the space on DRAM node for the hot PMEM pages to
be promoted to.  This has been implemented in this patchset too.

The patchset is based on the following not-yet-merged patchset,

[RFC][PATCH 0/9] [v3] Migrate Pages in lieu of discard
https://lkml.kernel.org/lkml/20200818184122.29C415DF@viggo.jf.intel.com/

This is part of a larger patch set.  If you want to apply these or
play with them, I'd suggest using the tree from below,

https://github.com/hying-caritas/linux/commits/autonuma-r3

We have tested the solution with the pmbench memory accessing
benchmark with the 80:20 read/write ratio and the normal access
address distribution on a 2 socket Intel server with Optane DC
Persistent Memory Model.  The test results of the base kernel and step
by step optimizations are as follows,

                Throughput	Promotion      DRAM bandwidth
		  access/s           MB/s                MB/s
               -----------     ----------      --------------
Base            63868367.1                             3626.7
Patch 1        137611105.1          353.5              8608.5
Patch 2        136124113.3          351.8              8480.7
Patch 3        160166665.7          208.2              9407.8
Patch 4        158461356.4          105.3              8790.0
Patch 5        163254205.3           73.6              8800.2

The whole patchset improves the benchmark score up to 155.6%.  The
basic AutoNUMA based optimization solution, the hot page selection
algorithm, and the threshold automatic adjustment algorithms improves
the performance or reduce the overhead (promotion MB/s) mostly.

Changelog:

v3:

- Move the rate limit control as late as possible per Mel Gorman's
  comments.

- Revise the hot page selection implementation to store page scan time
  in struct page.

- Code cleanup.

- Rebased on the latest page demotion patchset.

v2:

- Addressed comments for V1.

- Rebased on v5.5.

Best Regards,
Huang, Ying