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[v8,0/3] Speedup mremap on ppc64

Message ID 20210616045735.374532-1-aneesh.kumar@linux.ibm.com (mailing list archive)
Headers show
Series Speedup mremap on ppc64 | expand

Message

Aneesh Kumar K.V June 16, 2021, 4:57 a.m. UTC 
This patchset enables MOVE_PMD/MOVE_PUD support on power. This requires
the platform to support updating higher-level page tables without
updating page table entries. This also needs to invalidate the Page Walk
Cache on architecture supporting the same.

This patchset is dependent on
https://lore.kernel.org/linux-mm/20210616045239.370802-1-aneesh.kumar@linux.ibm.com/

Changes from v7:
* Split mremap fixes to a separate series

Changes from v6:
* Update ppc64 flush_tlb_range to invalidate page walk cache.
* Add patches to fix race between mremap and page out
* Add patch to fix build error with page table levels 2

Changes from v5:
* Drop patch mm/mremap: Move TLB flush outside page table lock
* Add fixes for race between optimized mremap and page out

Changes from v4:
* Change function name and arguments based on review feedback.

Changes from v3:
* Fix build error reported by kernel test robot
* Address review feedback.

Changes from v2:
* switch from using mmu_gather to flush_pte_tlb_pwc_range() 

Changes from v1:
* Rebase to recent upstream
* Fix build issues with tlb_gather_mmu changes



Aneesh Kumar K.V (3):
  mm/mremap: Allow arch runtime override
  powerpc/book3s64/mm: Update flush_tlb_range to flush page walk cache
  powerpc/mm: Enable HAVE_MOVE_PMD support

 .../include/asm/book3s/64/tlbflush-radix.h    |  2 +
 arch/powerpc/include/asm/tlb.h                |  6 +++
 arch/powerpc/mm/book3s64/radix_hugetlbpage.c  |  8 +++-
 arch/powerpc/mm/book3s64/radix_tlb.c          | 44 ++++++++++++-------
 arch/powerpc/platforms/Kconfig.cputype        |  2 +
 mm/mremap.c                                   | 15 ++++++-
 6 files changed, 58 insertions(+), 19 deletions(-)