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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id u13-20020a5d514d000000b003172510d19dsm2754302wrt.73.2023.07.27.11.56.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 11:56:00 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v2 0/4] riscv: tlb flush improvements Date: Thu, 27 Jul 2023 20:55:49 +0200 Message-Id: <20230727185553.980262-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Rspamd-Queue-Id: 167E01C000D X-Rspam-User: X-Stat-Signature: 68q6q5dx7ntwbo8hwokxk61yk6betmxr X-Rspamd-Server: rspam01 X-HE-Tag: 1690484162-966584 X-HE-Meta: U2FsdGVkX18t7BaqmAuYT8Pf68aFUiSYDuMV4SHajdfPaDi9g6OrMr1JPy/Bx7Vv79N60X+gjHv9XExYIut/daw1eVr3I+lGTWfM3xN0DpppiekweWIrDCwgc1S8NjpiMzg0nJjFsrrgtQusrpO7un+GDK0lYD6NGIAvppfNKG3VvLAcvhh5I/X/FgzDL3W/HP08n08qSX0JbNaVfybiPZMyWwrYcwOBQt7qXrccUDfAA5pjWV7xO4R/NWLeFK/Fa1peFtraZLvKdUjJleLfW7vZtLfM4wB/glZNjx+qusi/zznWm4I6lw56zkQQaInx6+4iN2gThnTGKYKypQ6XZFgVcmeDSm3z6M+ZYx1KlbHL1rffd84JdQe78B0NnsNqNMnbfpcZpfj0ka8vobgVRMOkhpcTg99ND/+mHvv+YDriqAD6pk20QztSry3oHJrjohKDiqpILKE851bhqLvxoBS7BxiW+gxfErcMMp3ahPIFJh7Z99QEX0qivrwF+k8uwKKvlCWmEr1Rdoa3LTdE+ilTlhTMp543g4WTZ83utamqB34GkEVOQ5Hd4adSVt/l1mO4APfVc08OFFjKNAC+SqUg6OlgMu3sjxIMZUJ0jVNbWDFpWBswCA5DHLrY+LG4r+IZbFAiZREIXSPCAzkHyraWfhQxyS54423rBcAA3q9ybjo0A9+EoCfXVSyAIaF0EWhYZKeELqo+z2W6bO6LnSAEjA9ubob5DRcrboESWKfNBNcFgcV302JZE9m27q3ErzduKPMV59+1DHaeTkHlj980s+FTwqtTyYdLVrRjjkFzCXPb/AFnokQVOvhMQByvFeIpY0zc8QvnMSlQOuMkkJs7u+Iekutf9UJ7U/RZ3X2q+M23xO7sUaSLdq05fuQroYZRMJhT+Ab+oDrUUsUzu7Gb4cpR99zJeJErxtxtQojIThN35ndStE1Vlkg9LkZ7NMLOZ34YILv26NeSHO6 fZ1BR/XL hzm1U8pMduz0XpxctEF0O3rxzkzvmKSUN1j+Lalf0uIAOPMPElzQvLR3wBo03e5pUEX0sDLZagF1ro6siGp1mxYRE5jvyrkxtKjLP9x5EjCWzPkl1HsOCQf/gp3Tm4C4Ha/Uk6mHB9JLPZlfQTpmIqZX3srKjyUCQXD/lOLajJm8345qIfujFTsZwWRgDE4FHbsSINADP0bOOEPDBd/ZmUH7sF+HzseH672dGkHwVhe8kvdCM4Gj0bRz5Vkz+BFGzNapPnCARf5cowa5rNdqTuNJ4zAYacY+sqSd830wqAuzVFPbA2FRdJCvf+4gIbgiBcBdpbu6lcR437MvFM1NEa/HD4542ctauTuyKD5lKrYn+X+iRn8OO+pHzbX2XSVE+4VqJoOkDx4hRO8R8/+UoI7ORSveMVIn+gFwtjqH5s2RL7K2S3PKbYHsyT8m4ePaxbiEEppbX5vu7VgV2uDehqztO+KMG7Eavp/Zx6XhgW0Odpt5enpaZj6G+khOF1hTRmtFC X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: This series optimizes the tlb flushes on riscv which used to simply flush the whole tlb whatever the size of the range to flush or the size of the stride. Patch 3 introduces a threshold that is microarchitecture specific and will very likely be modified by vendors, not sure though which mechanism we'll use to do that (dt? alternatives? vendor initialization code?). Next steps would be to implement: - svinval extension as Mayuresh did here [1] - BATCHED_UNMAP_TLB_FLUSH (I'll wait for arm64 patchset to land) - MMU_GATHER_RCU_TABLE_FREE - MMU_GATHER_MERGE_VMAS Any other idea welcome. [1] https://lore.kernel.org/linux-riscv/20230623123849.1425805-1-mchitale@ventanamicro.com/ Changes in v2: - Make static tlb_flush_all_threshold, we'll figure out later how to override this value on a vendor basis, as suggested by Conor and Palmer - Fix nommu build, as reported by Conor Alexandre Ghiti (4): riscv: Improve flush_tlb() riscv: Improve flush_tlb_range() for hugetlb pages riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb riscv: Improve flush_tlb_kernel_range() arch/riscv/include/asm/tlb.h | 8 ++- arch/riscv/include/asm/tlbflush.h | 12 ++-- arch/riscv/mm/tlbflush.c | 93 +++++++++++++++++++++++++++---- 3 files changed, 96 insertions(+), 17 deletions(-)