From patchwork Tue Aug 22 13:56:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13360850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 827F8EE49AF for ; Tue, 22 Aug 2023 14:03:05 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 9597090000C; Tue, 22 Aug 2023 10:03:04 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 909D8940026; Tue, 22 Aug 2023 10:03:04 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 7D17A900011; Tue, 22 Aug 2023 10:03:04 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id 6C82B90000C for ; Tue, 22 Aug 2023 10:03:04 -0400 (EDT) Received: from smtpin01.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay03.hostedemail.com (Postfix) with ESMTP id 2B3EAA02FB for ; Tue, 22 Aug 2023 14:03:04 +0000 (UTC) X-FDA: 81151907088.01.DC2430A Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by imf23.hostedemail.com (Postfix) with ESMTP id 20B44140017 for ; Tue, 22 Aug 2023 14:03:01 +0000 (UTC) Authentication-Results: imf23.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=gxEtJXOL; spf=pass (imf23.hostedemail.com: domain of broonie@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=broonie@kernel.org; dmarc=pass (policy=none) header.from=kernel.org ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1692712982; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding:in-reply-to: references:dkim-signature; bh=R/mskdT7+w487WaNzhbxyhU2mDnAdekowXGYzNkeqUA=; b=RsE78Y+HTJ4CxUtEvXLL/DY0gPXwdXPlvI6bp8D2yZ4YVtU1VM5vDBd2cFFCjvULwBphk3 jSCDooYsQA/GKjcVcHOSg7z2vORjx3gScAl7Fd7XuoUpKkPfzJvf0SCYjEtP7ItU/V6zwT B6cmqk08Ubo7PDzhNJ42rc31th+0rT0= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1692712982; a=rsa-sha256; cv=none; b=EWh+lPQxd0QyTuubBd4E9C1fJoTG/VCyPyTuekAVfz7dXsPO5MU4RvYTAI9AXn0u6dO4Pq L7yjLRQrP2Yd7kOV5MjXy8GsHz14N1DByBcCqUky/2qwAiXVsM/QJ+O+nkDfPUZgvxNzIU mPJMES+8EOfwk1g4VoBaixcKYK9sa1Y= ARC-Authentication-Results: i=1; imf23.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=gxEtJXOL; spf=pass (imf23.hostedemail.com: domain of broonie@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=broonie@kernel.org; dmarc=pass (policy=none) header.from=kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E61C362166; Tue, 22 Aug 2023 14:03:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3312BC433C7; Tue, 22 Aug 2023 14:02:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692712980; bh=0gvkuKR41LGGCd8avLTCcB5z1Ttp9harJ3mALBvT3Gw=; h=From:Subject:Date:To:Cc:From; b=gxEtJXOL1Hgyne57ipBABSTFa6QgcPoxLtH4o+/gaqp9R8cBMbILKQQHppJCVeqNd GbLzFzBrJt2g1yZtqaAiKAq3oBuFQOOIZ0QBrFFqKmhPDfX5ZFjGZ2NeNoIfKSkBEV V8UtWU0wG6g5rCxDfMwL5B6PR2qzrvs9FcbIaj+F2j1sSXv8qw4rrxUMM9lnn7CIwd 6pLwxiUHlvhMJEWaDdLq9+ak+XRE2B8Ru6ztsawq4IRsiqlASahr4SNsXx5WCAc50C 2wOvuNa6m6HUSXroXkpDmQVCOl6uNobz+xm6ezDIV3a7DbDlTKoKHy0v9daa+5k/Km xCGH3/Zugc95g== From: Mark Brown Subject: [PATCH v5 00/37] arm64/gcs: Provide support for GCS in userspace Date: Tue, 22 Aug 2023 14:56:33 +0100 Message-Id: <20230822-arm64-gcs-v5-0-9ef181dd6324@kernel.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAJK+5GQC/2XOy27DIBAF0F+JWJeKVzBklf+osuAx2CiNHUFkN bL87x27ixJFrO6Ic2cWUqFkqOR0WEiBOdc8jRiOHwcSBjf2QHPETAQTkuGjrty0on2oFCTnzrN oOmEJ/veuAvXFjWHYxON236b3Ain/7Bu+LpiHXB9Tee4LZ75N/7o7rpvumVNGfTrqLlnpvdPnK 5QRvj+n0pOtZhYNFaqlAmkMIvCoVBDg36hsqOQtlUhDjMkma1i05o2qf2pY11KFVJuQnMSTmbY vdF3XX2N1C0dqAQAA To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.13-dev-034f2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12491; i=broonie@kernel.org; h=from:subject:message-id; bh=0gvkuKR41LGGCd8avLTCcB5z1Ttp9harJ3mALBvT3Gw=; b=owGbwMvMwMWocq27KDak/QLjabUkhpQn+98/yF7BKauw0dr7UGezhMA5o6LOH8He2RybFGIqpS78 v3+0k9GYhYGRi0FWTJFl7bOMVenhElvnP5r/CmYQKxPIFAYuTgGYSBkr+x+OcIv/lzac/+IuxsucfW Zb4fSXOk8m7potuq733mnfLW5fV6ZqCUc/LZ5/0PXvRAbdLUqHFx3pYbnIYmXc+sMu1/DainS50v6S /8/41qYezJRddtJieu16IChVenArI1WwUHo5j7xYn1bxvHcZdzgVvhx8KPFH58SqmLtuOUd5H9kHxJ 5OnbTh8ffYg3Z7/pes8bnU/6KiasKb+H4WZo9fPaGRvfn/bbrimv5Y5y2MfzSl4kV38Yz6E3LbHnZa PbrhWhycveTFYVbDH5Ybf6az8n3zmvRwQRvTxh8Z5X//Rgkd+l+4rGOqgN4ahcAnqTYc5Ux3hCqFA0 9ZvH3U7D5X0+mxn7XU28kxnzl9AQ== X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-Rspamd-Queue-Id: 20B44140017 X-Rspam-User: X-Stat-Signature: pwkydjpo3bmhczdw67urqfjr7rt7z1cj X-Rspamd-Server: rspam03 X-HE-Tag: 1692712981-500024 X-HE-Meta: U2FsdGVkX198vhvsWRPJr/uhrR3Cf9yuEAxdvz0SXimWF6Da/LwrzQMtLKYOS0kWsYE6oaSJFVGS6MwkniiAWL2O+Kp/5aVquK2pkUvGJuIV4Z0Zr0WJIDhUXfqtpCIv8Hov3ffxI+TI1yJIML86iD29aiZvhZEKQFwCEpuxg1Wd/4+4FeqC34vFpgrpYWZWXgiPZ8Uf09oPp+BdDWprE8nz2iI/GSgVkMLtcSiwpglPHKs8ozEISy3v0WgX58R+XvjS1FAoK8PWRNdvIgvR/souWn9NzHYSuUHxYgEaxYyW5EtPBJKzzcZQ5dhccUogiEv/uCQ1fF/bumAZMcCQyV2uxvmRHh/dLqwCsQVilmjw+nFwjirUX6GHFSbyOHB4EyOHNWxo8FWi5bs09oR4FtEmUgq0bjLdaBbYpAiBXALMdn9R9za5pTDb4wDqBbpeKFGZTRvpdJOBTW28c5ADH0jICh743PJ2QaWFwP+KNGTs6V1rc295+dedOS7U7ifFCAoDzCXxPSbWQrXsiAnbyie3r8D55TutxQWBTuk0Qw4LgpmXmaHOGY+KHRYT2wnXmKloHLKdxkB6/PFgiaUGzukPaw+/iGSKlusHpwnju+8PIhhY1hTGbBhPKs0S/ksnUY+6ZoVZoMireFvdvgII6c6w2BFRj3hBozvnamg6F8tBdB4LPPEfcZf3525aoQ2j4Ny4wxiwtb9hR57EoE/+lJVilEoc313FPbTD9gUn3cdsx7YSBg3fL/eF2gyIoqlJkH2Eu5dz4br+I7cmYgGk5fHEhIdX/z6SWKQf6BbIU1cJQUs4a6rZw7ZQkppd2Ii5mxN/dIZaYPR4qvmH8u4JKKDHC369PiJSA7u2inlXFRUVMIPEuM9v+h0QAFZbpUD/fIGraY9gaR4I9KFNIARIiNbQsW+sqktqvuuYT8xcQa6QysX1h5CN9GLNWvs/O5L3N99sZVM/mUYg1ist7S6 d0rCrK4p mBGhXEQLkFX6jiPP02uAWBgohUJ4HzKP3lmjtk9Kw5ejHZYXh9sfP571H0gnZBC0QCdJisUiF3kqDtJp3RaAYz2lioH7KBIQ86I7GEj9HSSlWP8JXOHn3kEjwcew6ZdpQZ/iPVSOk2t3YaJPXD5PPQUbGL1ot35NpAAcNTQc8SUbXFEeHZuvsdk2LPVaF3psVYKq7zBbDUX3VlDJ4DciWTquy7g9l/CJ/DqMQlG7Eo+vUKviMrm/P3X4eF2JG0jFS8ybQcGDnZciD4gUcAF2b/WHwgtXxifFFQ5tETOKFqs8IGKzjz0HndwTibbCAdPx+YdsFam61bgfZ9u6w5QwtBtmCfYhcywt5T46qIalyeBzDN6sWzUHX2DPIlzin8ad2HCY2ozlkpQmHr36aiU+OZQ+OXPivRc1tHXZG7Osi1icfWZ7AEeMbvJseapmso596sPSeB1KdIhDwxWNSGnqWedu+uBtGG4lfZcBHKCcn7OOymXmBJOhx5n9aPTkER7W2m9Yv X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The arm64 Guarded Control Stack (GCS) feature provides support for hardware protected stacks of return addresses, intended to provide hardening against return oriented programming (ROP) attacks and to make it easier to gather call stacks for applications such as profiling. When GCS is active a secondary stack called the Guarded Control Stack is maintained, protected with a memory attribute which means that it can only be written with specific GCS operations. The current GCS pointer can not be directly written to by userspace. When a BL is executed the value stored in LR is also pushed onto the GCS, and when a RET is executed the top of the GCS is popped and compared to LR with a fault being raised if the values do not match. GCS operations may only be performed on GCS pages, a data abort is generated if they are not. The combination of hardware enforcement and lack of extra instructions in the function entry and exit paths should result in something which has less overhead and is more difficult to attack than a purely software implementation like clang's shadow stacks. This series implements support for use of GCS by userspace, along with support for use of GCS within KVM guests. It does not enable use of GCS by either EL1 or EL2, this will be implemented separately. Executables are started without GCS and must use a prctl() to enable it, it is expected that this will be done very early in application execution by the dynamic linker or other startup code. For dynamic linking this will be done by checking that everything in the executable is marked as GCS compatible. x86 has an equivalent feature called shadow stacks, this series depends on the x86 patches for generic memory management support for the new guarded/shadow stack page type and shares APIs as much as possible. As there has been extensive discussion with the wider community around the ABI for shadow stacks I have as far as practical kept implementation decisions close to those for x86, anticipating that review would lead to similar conclusions in the absence of strong reasoning for divergence. The main divergence I am concious of is that x86 allows shadow stack to be enabled and disabled repeatedly, freeing the shadow stack for the thread whenever disabled, while this implementation keeps the GCS allocated after disable but refuses to reenable it. This is to avoid races with things actively walking the GCS during a disable, we do anticipate that some systems will wish to disable GCS at runtime but are not aware of any demand for subsequently reenabling it. x86 uses an arch_prctl() to manage enable and disable, since only x86 and S/390 use arch_prctl() a generic prctl() was proposed[1] as part of a patch set for the equivalent RISC-V zisslpcfi feature which I initially adopted fairly directly but following review feedback has been revised quite a bit. There is an open issue with support for CRIU, on x86 this required the ability to set the GCS mode via ptrace. This series supports configuring mode bits other than enable/disable via ptrace but it needs to be confirmed if this is sufficient. There's a few bits where I'm not convinced with where I've placed things, in particular the GCS write operation is in the GCS header not in uaccess.h, I wasn't sure what was clearest there and am probably too close to the code to have a clear opinion. The reporting of GCS in /proc/PID/smaps is also a bit awkward. The series depends on the x86 shadow stack support: https://lore.kernel.org/lkml/20230227222957.24501-1-rick.p.edgecombe@intel.com/ I've rebased this onto v6.5-rc4 but not included it in the series in order to avoid confusion with Rick's work and cut down the size of the series, you can see the branch at: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc.git arm64-gcs [1] https://lore.kernel.org/lkml/20230213045351.3945824-1-debug@rivosinc.com/ Pending feedback from Catalin: - Switch copy_to_user_gcs() to be put_user_gcs(). Signed-off-by: Mark Brown --- Changes in v5: - Don't map any permissions for user GCSs, we always use EL0 accessors or use a separate mapping of the page. - Reduce the standard size of the GCS to RLIMIT_STACK/2. - Enforce a PAGE_SIZE alignment requirement on map_shadow_stack(). - Clarifications and fixes to documentation. - More tests. - Link to v4: https://lore.kernel.org/r/20230807-arm64-gcs-v4-0-68cfa37f9069@kernel.org Changes in v4: - Implement flags for map_shadow_stack() allowing the cap and end of stack marker to be enabled independently or not at all. - Relax size and alignment requirements for map_shadow_stack(). - Add more blurb explaining the advantages of hardware enforcement. - Link to v3: https://lore.kernel.org/r/20230731-arm64-gcs-v3-0-cddf9f980d98@kernel.org Changes in v3: - Rebase onto v6.5-rc4. - Add a GCS barrier on context switch. - Add a GCS stress test. - Link to v2: https://lore.kernel.org/r/20230724-arm64-gcs-v2-0-dc2c1d44c2eb@kernel.org Changes in v2: - Rebase onto v6.5-rc3. - Rework prctl() interface to allow each bit to be locked independently. - map_shadow_stack() now places the cap token based on the size requested by the caller not the actual space allocated. - Mode changes other than enable via ptrace are now supported. - Expand test coverage. - Various smaller fixes and adjustments. - Link to v1: https://lore.kernel.org/r/20230716-arm64-gcs-v1-0-bf567f93bba6@kernel.org --- Mark Brown (37): arm64/mm: Restructure arch_validate_flags() for extensibility prctl: arch-agnostic prctl for shadow stack arm64: Document boot requirements for Guarded Control Stacks arm64/gcs: Document the ABI for Guarded Control Stacks arm64/sysreg: Add new system registers for GCS arm64/sysreg: Add definitions for architected GCS caps arm64/gcs: Add manual encodings of GCS instructions arm64/gcs: Provide copy_to_user_gcs() arm64/cpufeature: Runtime detection of Guarded Control Stack (GCS) arm64/mm: Allocate PIE slots for EL0 guarded control stack mm: Define VM_SHADOW_STACK for arm64 when we support GCS arm64/mm: Map pages for guarded control stack KVM: arm64: Manage GCS registers for guests arm64/gcs: Allow GCS usage at EL0 and EL1 arm64/idreg: Add overrride for GCS arm64/hwcap: Add hwcap for GCS arm64/traps: Handle GCS exceptions arm64/mm: Handle GCS data aborts arm64/gcs: Context switch GCS state for EL0 arm64/gcs: Allocate a new GCS for threads with GCS enabled arm64/gcs: Implement shadow stack prctl() interface arm64/mm: Implement map_shadow_stack() arm64/signal: Set up and restore the GCS context for signal handlers arm64/signal: Expose GCS state in signal frames arm64/ptrace: Expose GCS via ptrace and core files arm64: Add Kconfig for Guarded Control Stack (GCS) kselftest/arm64: Verify the GCS hwcap kselftest/arm64: Add GCS as a detected feature in the signal tests kselftest/arm64: Add framework support for GCS to signal handling tests kselftest/arm64: Allow signals tests to specify an expected si_code kselftest/arm64: Always run signals tests with GCS enabled kselftest/arm64: Add very basic GCS test program kselftest/arm64: Add a GCS test program built with the system libc kselftest/arm64: Add test coverage for GCS mode locking selftests/arm64: Add GCS signal tests kselftest/arm64: Add a GCS stress test kselftest/arm64: Enable GCS for the FP stress tests Documentation/admin-guide/kernel-parameters.txt | 3 + Documentation/arch/arm64/booting.rst | 22 + Documentation/arch/arm64/elf_hwcaps.rst | 3 + Documentation/arch/arm64/gcs.rst | 233 +++++++ Documentation/arch/arm64/index.rst | 1 + Documentation/filesystems/proc.rst | 2 +- arch/arm64/Kconfig | 19 + arch/arm64/include/asm/cpufeature.h | 6 + arch/arm64/include/asm/el2_setup.h | 17 + arch/arm64/include/asm/esr.h | 28 +- arch/arm64/include/asm/exception.h | 2 + arch/arm64/include/asm/gcs.h | 106 +++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/asm/kvm_arm.h | 4 +- arch/arm64/include/asm/kvm_host.h | 12 + arch/arm64/include/asm/mman.h | 20 +- arch/arm64/include/asm/pgtable-prot.h | 14 +- arch/arm64/include/asm/processor.h | 7 + arch/arm64/include/asm/sysreg.h | 20 + arch/arm64/include/asm/uaccess.h | 42 ++ arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/ptrace.h | 8 + arch/arm64/include/uapi/asm/sigcontext.h | 9 + arch/arm64/kernel/cpufeature.c | 19 + arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/kernel/entry-common.c | 23 + arch/arm64/kernel/idreg-override.c | 2 + arch/arm64/kernel/process.c | 89 +++ arch/arm64/kernel/ptrace.c | 59 ++ arch/arm64/kernel/signal.c | 237 ++++++- arch/arm64/kernel/traps.c | 11 + arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 17 + arch/arm64/kvm/sys_regs.c | 22 + arch/arm64/mm/Makefile | 1 + arch/arm64/mm/fault.c | 79 ++- arch/arm64/mm/gcs.c | 225 +++++++ arch/arm64/mm/mmap.c | 13 +- arch/arm64/tools/cpucaps | 1 + arch/arm64/tools/sysreg | 55 ++ fs/proc/task_mmu.c | 3 + include/linux/mm.h | 16 +- include/linux/syscalls.h | 1 + include/uapi/asm-generic/unistd.h | 5 +- include/uapi/linux/elf.h | 1 + include/uapi/linux/prctl.h | 22 + kernel/sys.c | 30 + kernel/sys_ni.c | 1 + tools/testing/selftests/arm64/Makefile | 2 +- tools/testing/selftests/arm64/abi/hwcap.c | 19 + tools/testing/selftests/arm64/fp/assembler.h | 15 + tools/testing/selftests/arm64/fp/fpsimd-test.S | 2 + tools/testing/selftests/arm64/fp/sve-test.S | 2 + tools/testing/selftests/arm64/fp/za-test.S | 2 + tools/testing/selftests/arm64/fp/zt-test.S | 2 + tools/testing/selftests/arm64/gcs/.gitignore | 5 + tools/testing/selftests/arm64/gcs/Makefile | 24 + tools/testing/selftests/arm64/gcs/asm-offsets.h | 0 tools/testing/selftests/arm64/gcs/basic-gcs.c | 356 ++++++++++ tools/testing/selftests/arm64/gcs/gcs-locking.c | 200 ++++++ .../selftests/arm64/gcs/gcs-stress-thread.S | 311 +++++++++ tools/testing/selftests/arm64/gcs/gcs-stress.c | 532 +++++++++++++++ tools/testing/selftests/arm64/gcs/gcs-util.h | 100 +++ tools/testing/selftests/arm64/gcs/libc-gcs.c | 742 +++++++++++++++++++++ tools/testing/selftests/arm64/signal/.gitignore | 1 + .../testing/selftests/arm64/signal/test_signals.c | 17 +- .../testing/selftests/arm64/signal/test_signals.h | 6 + .../selftests/arm64/signal/test_signals_utils.c | 32 +- .../selftests/arm64/signal/test_signals_utils.h | 39 ++ .../arm64/signal/testcases/gcs_exception_fault.c | 59 ++ .../selftests/arm64/signal/testcases/gcs_frame.c | 78 +++ .../arm64/signal/testcases/gcs_write_fault.c | 67 ++ .../selftests/arm64/signal/testcases/testcases.c | 7 + .../selftests/arm64/signal/testcases/testcases.h | 1 + 73 files changed, 4096 insertions(+), 38 deletions(-) --- base-commit: e514f673179ed8af6c64d79f8d43e2569ad6cb9f change-id: 20230303-arm64-gcs-e311ab0d8729 Best regards,