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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id l10-20020a5d560a000000b0032f7865a4c7sm1983318wrv.21.2023.11.10.06.07.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Nov 2023 06:07:22 -0800 (PST) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Dmitry Vyukov , Vincenzo Frascino , Arnd Bergmann , Dennis Zhou , Tejun Heo , Christoph Lameter , Andrew Morton , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-arch@vger.kernel.org, linux-mm@kvack.org Cc: Alexandre Ghiti Subject: [PATCH 0/2] riscv: Enable percpu page first chunk allocator Date: Fri, 10 Nov 2023 15:07:19 +0100 Message-Id: <20231110140721.114235-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 1A4D0180006 X-Stat-Signature: gznjjwgkj7oqoijmszsikrmgtft7hipy X-Rspam-User: X-HE-Tag: 1699625244-766990 X-HE-Meta: U2FsdGVkX1+SziUgi3I3nwUlGHIx3SXWrTV45AVxqEc81d3vbqhTgN4JvNJ+v7ZitehkboZMS1ztn3O5nUDYlakYLodc5eQQHl4QZgOZ/mZB9PlGNpDZFr4j2yHBb+/PuOBj0av1fTEkJaoFGIIWSGe0NWFqO1oRdprBS3su0aoNNuHoW4USYReOQjyXBr2Fw08ortRDJAayN52z1aNGkFCX+HcHvAg+G8SSrs0fiOkxvG7y4h3ZYMyWzniilFCeCcezfowXTs9lJB+DNX+/geQ0Q59q4rh8K+60eLHah0kF9lkruOl6ZkscPke914DEpe83mJSp4u/cYSb/3CONmZG2kMXoDsnLTjZfqPpUcsAoCYJAxt6eTwIIgO+GNPdNpe7xCNl0OAQYfUV2JSWPTPP5hDCO1szwH1cIlspPNIOlWoKcEtiMuac2HJLEsCRiMEz09Mcgf4EIiE8jbsYUEZtd3GoVkvNv3mCLtf/2jeh2jZOyzVz9GwascqRlT8fJ0QXeDAxhkdq14dTyYqkrDXi9lvn2OqMhWyrOZHSeBWI+gICZp2abeg5YJutnS876K5j7S070UoaaiZ5tg6wYfDF23/QfX0oz1992nMQOhVCoWevipW2GyQvZM+LSFhrtACkWYF8EzY3PDafpCMYXTrZ2mTf8rAZsi4Bt4yFaHwNBntKvUCX+u1jMvOSJA2CO08babDdp4v7tE8DN8nzv05QEv2mWYxHRsOh8xJf9/AI0MsNF+SNXotja2vHvFsl1vSBReS3EzmJG4JWny5dyCoMa33/6tkrgCWzkW0ZJ5/UtQ7SuoxzmM++d8OkX36zRnqIIMlyAN9zDj3xL/Vw9C9keb6j3Zs+N3byQotlA5ZNx6rqbc+RWij9th0yy2HAMEfNSYc1a9d+E/6brSInEQ0FDkW3uL2c58R9JPahTljMuuTubJdywoSk5+/tUpPzGvqwX5Ya95gtPxTWLfVY eSty11Zr bZw3GVilN0ObMb0324+L0rFwz61flBZXJvXDJXxioAcQbnbS02vv8nuIecQjouPptvD/xNg4mFWWliuqyw4Qo5y3BqUrusBmiYz3JIRJg9N0+NdwVrEa/e188roZNxrHA5Dkb6pS2ktOs2SBjaPVjp4nE1VNY/1/ZXOnAF8uQBuIvAcBvfeC3V3cwjbqxqRuklcCyTrQQCm2+tRKJe88wkHs9JHcZoYx5/h26uFlP/S4gVZXkaqsUVXXbzxlRI4MfI7Xt3R2z3Ox912kQGG6oy0eODjmMBhXuPWJJswtmxYqGB7tcmwpzLTAd6aFJOUKEuGW09Wi4NByjtsQ6fOj8THFjPY7hc8zHc4uf4Rlzt/ExkvWRd9/64ZfFUmKyGJ+NfaW7XTsTRkWr13kTqxSJwztZvndKgT5Aq9Z7D2W7MlZILWJ6aNsyRrbQRcpnThwCKBDaOGPdi/yJR3Iz0PCfzEtbXxeLpxKC9DBv21Gr/eSoyUtVjqLfnqZrp0bg2pLLq3OK X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: While working with pcpu variables, I noticed that riscv did not support first chunk allocation in the vmalloc area which may be needed as a fallback in case of a sparse NUMA configuration. patch 1 starts by introducing a new function flush_cache_vmap_early() which is needed since a new vmalloc mapping is established and directly accessed: on riscv, this would likely fail in case of a reordered access or if the uarch caches invalid entries in TLB. patch 2 simply enables the page percpu first chunk allocator in riscv. Alexandre Ghiti (2): mm: Introduce flush_cache_vmap_early() and its riscv implementation riscv: Enable pcpu page first chunk allocator arch/riscv/Kconfig | 2 ++ arch/riscv/include/asm/cacheflush.h | 3 ++- arch/riscv/include/asm/tlbflush.h | 2 ++ arch/riscv/mm/kasan_init.c | 8 ++++++++ arch/riscv/mm/tlbflush.c | 5 +++++ include/asm-generic/cacheflush.h | 6 ++++++ mm/percpu.c | 8 +------- 7 files changed, 26 insertions(+), 8 deletions(-)