From patchwork Mon Jun 4 23:12:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 10447473 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 729FE603D7 for ; Mon, 4 Jun 2018 23:22:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 64F2829222 for ; Mon, 4 Jun 2018 23:22:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 59BCD29227; Mon, 4 Jun 2018 23:22:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B311829226 for ; Mon, 4 Jun 2018 23:22:22 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 877A36B026D; Mon, 4 Jun 2018 19:22:21 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 84EE96B026E; Mon, 4 Jun 2018 19:22:21 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 768066B026F; Mon, 4 Jun 2018 19:22:21 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from mail-pl0-f72.google.com (mail-pl0-f72.google.com [209.85.160.72]) by kanga.kvack.org (Postfix) with ESMTP id 32FDF6B026D for ; Mon, 4 Jun 2018 19:22:21 -0400 (EDT) Received: by mail-pl0-f72.google.com with SMTP id bb11-v6so230352plb.15 for ; Mon, 04 Jun 2018 16:22:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-original-authentication-results:x-gm-message-state:subject:from :to:cc:date:message-id:in-reply-to:references:user-agent :mime-version:content-transfer-encoding; bh=1vAnDNepZJNFQqYKJpVg1im/vcxxepXM84YkiJCClQw=; b=ZKXEhgF5DdSOIty19UjrTM8mVtqBGjLLKvuGoTLtWYkMfGpPoyU1ulm4oJCbVvJLac xPSPaiEUfZOjocRPTqxTnCYeeLyKi0EDFkI7SXfW8n1JXbhrRVdP2oDC0EcXnZuxQb7f 6BpvZE+p4XY5yQVe5pzMR6wX3PGJm+CwmOkKTw3YlUs350ZzaSeWiJVguP1PAOeVRzGY JqKrmDsV7Y+Jp2dFJCn4pd7Hl35XTGQm9gc0bkjCmfTNoNNSql6+b0hURHnFigFL1rvd dlE0llgvNner2p8Ci4OJR4mqGEc7mJ618yezlMiVL1Mt3ApatYy1J/b9WaEhyYrtRUzd n5JA== X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of dan.j.williams@intel.com designates 192.55.52.93 as permitted sender) smtp.mailfrom=dan.j.williams@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Gm-Message-State: ALKqPwdbCLSvo6qd4+Xh7vOrWt6Dqjm0HVLQ+TIEql/MDLa3lM/o0ayX JnddBryjtF8Df3kaKtWj3CZ8XCSgGnnd2gy7begINC716Jl0qXsHTHmV0WC0bnGV6Kr81A3JBNl Ya5P2Tk8KZeCwpKSZ2D2hPl0qsZDqEGQTfLE8tHpU19UFYdRdx5iOX9EgHDbmBEMKfg== X-Received: by 2002:a63:7847:: with SMTP id t68-v6mr11190339pgc.329.1528154540842; Mon, 04 Jun 2018 16:22:20 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJoN0qlv7qtap+AmKAhL6ILr9WvLqajf2EUhh9As9incExb2c0EZ7XD1vBTyiZNH1UOKTlQ X-Received: by 2002:a63:7847:: with SMTP id t68-v6mr11190305pgc.329.1528154539868; Mon, 04 Jun 2018 16:22:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528154539; cv=none; d=google.com; s=arc-20160816; b=lehB0whl1PM0MrCj5dNW6oCOJ+Dc9THd9eMUXyLSS3TaSlOQE/0DNMod642mdbp1uU UmnfLlx2lksWDdicN38EHKW4nWKF9l62zv12SgHPOzpeu5UlhepxoZW8s8ogJQhPkAij oNXyf5FENLbtUUD26HRyuwuMPHDoV4D340MaJx0QfhO5JZV6OJnD6wDiIbH58QCs3aFn W/Lgt0Ei3vv1iIw9WEpu/sNvu0Rk5lFuOkK8CnVvBsH0l/PCzbeQXi90POZ8qLMEUqhS bpuYvgrNUHEuTr6itj/gmXkmuPCAyzjsCcyeywIM7FVFTpa/t10XwFhU4BZhcsNojXvW Qpdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:user-agent:references :in-reply-to:message-id:date:cc:to:from:subject :arc-authentication-results; bh=1vAnDNepZJNFQqYKJpVg1im/vcxxepXM84YkiJCClQw=; b=v+vM8+cdyhfwsim+6btGveB9qFmaTgAmner1wRkhja+DHT6QauJCsUeze6v3O3lw61 NgExpcxBylDm4SKmprqhurAqUDS5xtxKJzaABqu6iilYGKDmnhd6/GLtEfcWSrXkYEZl nHsHon25bxEXXgyP422tdd/l213Sy8l+UuibqmI63qhUVcKd2FzP+Zgv28eQffZKf7We XkDthuKV62oUgMK4y4wqoyPx2S2wJPw6z+SBIx2r5YYKHV8d+e/9FZmkNTsgJeN3GysF 7EjqYTS85Jk3wGUD6UspddapUChOoF/9MM4UiYAhr3kv6+jTaGfPFl0si5UdQS0OWAWo uNlw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dan.j.williams@intel.com designates 192.55.52.93 as permitted sender) smtp.mailfrom=dan.j.williams@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from mga11.intel.com (mga11.intel.com. [192.55.52.93]) by mx.google.com with ESMTPS id q17-v6si18123973pgc.270.2018.06.04.16.22.19 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jun 2018 16:22:19 -0700 (PDT) Received-SPF: pass (google.com: domain of dan.j.williams@intel.com designates 192.55.52.93 as permitted sender) client-ip=192.55.52.93; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dan.j.williams@intel.com designates 192.55.52.93 as permitted sender) smtp.mailfrom=dan.j.williams@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Jun 2018 16:22:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,477,1520924400"; d="scan'208";a="229904634" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.16]) by orsmga005.jf.intel.com with ESMTP; 04 Jun 2018 16:22:19 -0700 Subject: [PATCH v3 08/12] x86/memory_failure: Introduce {set, clear}_mce_nospec() From: Dan Williams To: linux-nvdimm@lists.01.org Cc: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Tony Luck , Borislav Petkov , linux-edac@vger.kernel.org, x86@kernel.org, hch@lst.de, linux-mm@kvack.org, linux-fsdevel@vger.kernel.org, jack@suse.cz Date: Mon, 04 Jun 2018 16:12:22 -0700 Message-ID: <152815394224.39010.16927947197432406234.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <152815389835.39010.13253559944508110923.stgit@dwillia2-desk3.amr.corp.intel.com> References: <152815389835.39010.13253559944508110923.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-2-gc94f MIME-Version: 1.0 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP Currently memory_failure() returns zero if the error was handled. On that result mce_unmap_kpfn() is called to zap the page out of the kernel linear mapping to prevent speculative fetches of potentially poisoned memory. However, in the case of dax mapped devmap pages the page may be in active permanent use by the device driver, so it cannot be unmapped from the kernel. Instead of marking the page not present, marking the page UC should be sufficient for preventing poison from being pre-fetched into the cache. Convert mce_unmap_pfn() to set_mce_nospec() remapping the page as UC, to hide it from speculative accesses. Given that that persistent memory errors can be cleared by the driver, include a facility to restore the page to cacheable operation, clear_mce_nospec(). Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: Tony Luck Cc: Borislav Petkov Cc: Cc: Signed-off-by: Dan Williams --- arch/x86/include/asm/set_memory.h | 42 +++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mcheck/mce-internal.h | 15 ---------- arch/x86/kernel/cpu/mcheck/mce.c | 38 ++------------------------ include/linux/set_memory.h | 14 ++++++++++ 4 files changed, 59 insertions(+), 50 deletions(-) diff --git a/arch/x86/include/asm/set_memory.h b/arch/x86/include/asm/set_memory.h index bd090367236c..cf5e9124b45e 100644 --- a/arch/x86/include/asm/set_memory.h +++ b/arch/x86/include/asm/set_memory.h @@ -88,4 +88,46 @@ extern int kernel_set_to_readonly; void set_kernel_text_rw(void); void set_kernel_text_ro(void); +#ifdef CONFIG_X86_64 +static inline int set_mce_nospec(unsigned long pfn) +{ + unsigned long decoy_addr; + int rc; + + /* + * Mark the linear address as UC to make sure we don't log more + * errors because of speculative access to the page. + * We would like to just call: + * set_memory_uc((unsigned long)pfn_to_kaddr(pfn), 1); + * but doing that would radically increase the odds of a + * speculative access to the poison page because we'd have + * the virtual address of the kernel 1:1 mapping sitting + * around in registers. + * Instead we get tricky. We create a non-canonical address + * that looks just like the one we want, but has bit 63 flipped. + * This relies on set_memory_uc() properly sanitizing any __pa() + * results with __PHYSICAL_MASK or PTE_PFN_MASK. + */ + decoy_addr = (pfn << PAGE_SHIFT) + (PAGE_OFFSET ^ BIT(63)); + + rc = set_memory_uc(decoy_addr, 1); + if (rc) + pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn); + return rc; +} +#define set_mce_nospec set_mce_nospec + +/* Restore full speculative operation to the pfn. */ +static inline int clear_mce_nospec(unsigned long pfn) +{ + return set_memory_wb((unsigned long) pfn_to_kaddr(pfn), 1); +} +#define clear_mce_nospec clear_mce_nospec +#else +/* + * Few people would run a 32-bit kernel on a machine that supports + * recoverable errors because they have too much memory to boot 32-bit. + */ +#endif + #endif /* _ASM_X86_SET_MEMORY_H */ diff --git a/arch/x86/kernel/cpu/mcheck/mce-internal.h b/arch/x86/kernel/cpu/mcheck/mce-internal.h index 374d1aa66952..ceb67cd5918f 100644 --- a/arch/x86/kernel/cpu/mcheck/mce-internal.h +++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h @@ -113,21 +113,6 @@ static inline void mce_register_injector_chain(struct notifier_block *nb) { } static inline void mce_unregister_injector_chain(struct notifier_block *nb) { } #endif -#ifndef CONFIG_X86_64 -/* - * On 32-bit systems it would be difficult to safely unmap a poison page - * from the kernel 1:1 map because there are no non-canonical addresses that - * we can use to refer to the address without risking a speculative access. - * However, this isn't much of an issue because: - * 1) Few unmappable pages are in the 1:1 map. Most are in HIGHMEM which - * are only mapped into the kernel as needed - * 2) Few people would run a 32-bit kernel on a machine that supports - * recoverable errors because they have too much memory to boot 32-bit. - */ -static inline void mce_unmap_kpfn(unsigned long pfn) {} -#define mce_unmap_kpfn mce_unmap_kpfn -#endif - struct mca_config { bool dont_log_ce; bool cmci_disabled; diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 42cf2880d0ed..a0fbf0a8b7e6 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include @@ -50,7 +51,6 @@ #include #include #include -#include #include "mce-internal.h" @@ -108,10 +108,6 @@ static struct irq_work mce_irq_work; static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); -#ifndef mce_unmap_kpfn -static void mce_unmap_kpfn(unsigned long pfn); -#endif - /* * CPU/chipset specific EDAC code can register a notifier call here to print * MCE errors in a human-readable form. @@ -602,7 +598,7 @@ static int srao_decode_notifier(struct notifier_block *nb, unsigned long val, if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) { pfn = mce->addr >> PAGE_SHIFT; if (!memory_failure(pfn, 0)) - mce_unmap_kpfn(pfn); + set_mce_nospec(pfn); } return NOTIFY_OK; @@ -1070,38 +1066,10 @@ static int do_memory_failure(struct mce *m) if (ret) pr_err("Memory error not recovered"); else - mce_unmap_kpfn(m->addr >> PAGE_SHIFT); + set_mce_nospec(m->addr >> PAGE_SHIFT); return ret; } -#ifndef mce_unmap_kpfn -static void mce_unmap_kpfn(unsigned long pfn) -{ - unsigned long decoy_addr; - - /* - * Unmap this page from the kernel 1:1 mappings to make sure - * we don't log more errors because of speculative access to - * the page. - * We would like to just call: - * set_memory_np((unsigned long)pfn_to_kaddr(pfn), 1); - * but doing that would radically increase the odds of a - * speculative access to the poison page because we'd have - * the virtual address of the kernel 1:1 mapping sitting - * around in registers. - * Instead we get tricky. We create a non-canonical address - * that looks just like the one we want, but has bit 63 flipped. - * This relies on set_memory_np() not checking whether we passed - * a legal address. - */ - - decoy_addr = (pfn << PAGE_SHIFT) + (PAGE_OFFSET ^ BIT(63)); - - if (set_memory_np(decoy_addr, 1)) - pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn); -} -#endif - /* * The actual machine check handler. This only handles real * exceptions when something got corrupted coming in through int 18. diff --git a/include/linux/set_memory.h b/include/linux/set_memory.h index da5178216da5..2a986d282a97 100644 --- a/include/linux/set_memory.h +++ b/include/linux/set_memory.h @@ -17,6 +17,20 @@ static inline int set_memory_x(unsigned long addr, int numpages) { return 0; } static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; } #endif +#ifndef set_mce_nospec +static inline int set_mce_nospec(unsigned long pfn) +{ + return 0; +} +#endif + +#ifndef clear_mce_nospec +static inline int clear_mce_nospec(unsigned long pfn) +{ + return 0; +} +#endif + #ifndef CONFIG_ARCH_HAS_MEM_ENCRYPT static inline int set_memory_encrypted(unsigned long addr, int numpages) {