From patchwork Wed Jul 11 11:29:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joerg Roedel X-Patchwork-Id: 10519417 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B05136054E for ; Wed, 11 Jul 2018 11:30:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B4FDC28813 for ; Wed, 11 Jul 2018 11:30:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A90BF28D2E; Wed, 11 Jul 2018 11:30:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B002D28D38 for ; Wed, 11 Jul 2018 11:30:14 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 083106B026F; Wed, 11 Jul 2018 07:30:07 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 00C246B0270; Wed, 11 Jul 2018 07:30:06 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id DC6D76B0271; Wed, 11 Jul 2018 07:30:06 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by kanga.kvack.org (Postfix) with ESMTP id 7F69C6B026F for ; Wed, 11 Jul 2018 07:30:06 -0400 (EDT) Received: by mail-ed1-f71.google.com with SMTP id d30-v6so4533045edd.0 for ; Wed, 11 Jul 2018 04:30:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:dkim-signature:from:to:cc:subject:date :message-id:in-reply-to:references; bh=UEznKuSZaMJ6AsH0FJoohsPpgFrUgGLh2mNGRgHrb1Q=; b=kXFZrIoVoXGvvjy/S3XShg2FDoO9ow87VNz6HRVoL0H8MjtPo8jN/kun6wKZkp4MTV X8hEAb7YJb5zDLNUDbAPmTkhE9WpRfNchgXJdYBT6oYIN/4w3jqREhISPCTYb8ggi+ZA gFrHiF/F29t/NFQqN12E+8yziw/A1AuUOFfgca44KsfRN7I8/uVlgB1ETuLllK6HgEaG eOBYhKpyhA2QGP5GSV6vr3xPNwrtWsvvDpS5HV4Q0itioBKWhJ8BibxBF78zpnISfOr7 S8C79GPO8Lvh4GifD0MBGEhPP+wSpwxfZql5HM30WyCAmYQ2p7Gw4kTQeYB87ym0HSPj BWvA== X-Gm-Message-State: APt69E3fV6DyFfxcaO5n6gZ28nhtini+ei8nSeZzNV5n/E/nbwcZTy4c Nc9Ig04T/icBOXmfNitVrsRI7uELohSRnri8GGO/r/uSmzaU4Egkbt2jxR88ZV8+w8IMDKYyWvn yVLLqlqNibNgq3d5nw71wo4mvI+6Ey/HJJOOa9eqCBZulRQEzf2hDVWbLsY5NLXw2eQ== X-Received: by 2002:a50:94c4:: with SMTP id t4-v6mr30268966eda.128.1531308606062; Wed, 11 Jul 2018 04:30:06 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcwUsqmLxSfs4jMi4Av9prutMRIT+zvsb7krm57HdOY+vgTYu+Lfbp/FMJVK7DZIeAUgHSl X-Received: by 2002:a50:94c4:: with SMTP id t4-v6mr30268925eda.128.1531308605348; Wed, 11 Jul 2018 04:30:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531308605; cv=none; d=google.com; s=arc-20160816; b=hbpIL4OcmggmtZdQASK8xARpHuhOB9eUxHQpWzxnIM9myq0vpKzZbpPjuZoa8S/SUH 9l8OT53eTvYDrsedm2ieX3J4JnScPSFv8Ficfih+B+iNfBAZuToJMIpHplIU68dnF2AZ 0G3TsDqnAT8Dx6FWkI+CLXEeRYG6DEv/IdLosi9DMai/L6++aeKHpK2Pu50WJdp8gT1T FPg3TQlyqCse3og8IWW1JbK0MyuDSaMpIeBEEjytIQFjarPibvQSywFUM21YYtJTMjGw ueN3pW5xIeNNaFLsqHuC0wu1a3UpnfuM1qKaBVRfEnbeZ28dPxy94KFGveRNMGTPffFe GM2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=UEznKuSZaMJ6AsH0FJoohsPpgFrUgGLh2mNGRgHrb1Q=; b=jdZ5/Z92rQh6YB/H81Gtvpj+yuQw7M0MVlb67ymBUnKwXKzhE7rkE6ukHOBJ+llj8C yEast4Cv5MNJ9ZZj5QjmAp0CtPisZnGrJ4++xtFoiqu27/Oehmu5GYRiLJqUYtRtyO5E 4jx8zjMBFX59Tit3omL9Z7QDUk29xjQME5xYrk4jIa4KKjqt1XFvuI4RxRCaB09HoKOm gav3NObRJXitqNsUxPn/l4ND/nwod1d8geSBN/sPplpRMvm4NbQI07A8J+VO312evyd8 Zx178D+Yu8SSR3O95SNkB01riXw3fwAMqtwbfpwyFfTJiJRbwnDgGkMS0mAXSbypu9gQ dh/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass (test mode) header.i=@8bytes.org header.s=mail-1 header.b=crWKVDRD; spf=pass (google.com: domain of joro@8bytes.org designates 2a01:238:4383:600:38bc:a715:4b6d:a889 as permitted sender) smtp.mailfrom=joro@8bytes.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=8bytes.org Received: from theia.8bytes.org (8bytes.org. [2a01:238:4383:600:38bc:a715:4b6d:a889]) by mx.google.com with ESMTPS id b11-v6si568638edf.140.2018.07.11.04.30.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Jul 2018 04:30:05 -0700 (PDT) Received-SPF: pass (google.com: domain of joro@8bytes.org designates 2a01:238:4383:600:38bc:a715:4b6d:a889 as permitted sender) client-ip=2a01:238:4383:600:38bc:a715:4b6d:a889; Authentication-Results: mx.google.com; dkim=pass (test mode) header.i=@8bytes.org header.s=mail-1 header.b=crWKVDRD; spf=pass (google.com: domain of joro@8bytes.org designates 2a01:238:4383:600:38bc:a715:4b6d:a889 as permitted sender) smtp.mailfrom=joro@8bytes.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=8bytes.org Received: by theia.8bytes.org (Postfix, from userid 1000) id EC44F5BB; Wed, 11 Jul 2018 13:29:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=8bytes.org; s=mail-1; t=1531308599; bh=6bfJ1yD4EqIh0SLTKG6nHvS6Tbjr9DxGgwLNYwVUtAo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=crWKVDRD1dei+2h1W2WAT9KuWkYcMVOkqmfM/WxR4G3RJf6+MjjaUH57m5rX2Zzq4 X/cIgtQaX+bKm6OqBm1h/r1IJAfgCmwsIn5KRiqITvc/T6QP0ZiOWy+ul/3BXZrRm+ L95wcoJHpNakt63x2tRZKxOK6IvbCcI9lTMNApko+rpy9RkTHdsr5gVNc3qv34uHPM sI8JzSpxOPSEwH7hfgIOtajGfBnKPOvCHkDTciKrXV9pUF8QcB2e/Jii0wpX8ntueA 9bYV+tBc+Urf2Zj50xpCSf+JvxFTtlkhcQ76Z2sIg3oUCCo1vTBqbdJn90O9luuS/u TDNi2hqHGIphQ== From: Joerg Roedel To: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Linus Torvalds , Andy Lutomirski , Dave Hansen , Josh Poimboeuf , Juergen Gross , Peter Zijlstra , Borislav Petkov , Jiri Kosina , Boris Ostrovsky , Brian Gerst , David Laight , Denys Vlasenko , Eduardo Valentin , Greg KH , Will Deacon , aliguori@amazon.com, daniel.gruss@iaik.tugraz.at, hughd@google.com, keescook@google.com, Andrea Arcangeli , Waiman Long , Pavel Machek , "David H . Gutteridge" , jroedel@suse.de, joro@8bytes.org Subject: [PATCH 04/39] x86/entry/32: Put ESPFIX code into a macro Date: Wed, 11 Jul 2018 13:29:11 +0200 Message-Id: <1531308586-29340-5-git-send-email-joro@8bytes.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531308586-29340-1-git-send-email-joro@8bytes.org> References: <1531308586-29340-1-git-send-email-joro@8bytes.org> X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP From: Joerg Roedel This makes it easier to split up the shared iret code path. Signed-off-by: Joerg Roedel --- arch/x86/entry/entry_32.S | 97 ++++++++++++++++++++++++----------------------- 1 file changed, 49 insertions(+), 48 deletions(-) diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S index 39fdda3..d35a69a 100644 --- a/arch/x86/entry/entry_32.S +++ b/arch/x86/entry/entry_32.S @@ -221,6 +221,54 @@ POP_GS_EX .endm +.macro CHECK_AND_APPLY_ESPFIX +#ifdef CONFIG_X86_ESPFIX32 +#define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8) + + ALTERNATIVE "jmp .Lend_\@", "", X86_BUG_ESPFIX + + movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS + /* + * Warning: PT_OLDSS(%esp) contains the wrong/random values if we + * are returning to the kernel. + * See comments in process.c:copy_thread() for details. + */ + movb PT_OLDSS(%esp), %ah + movb PT_CS(%esp), %al + andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax + cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax + jne .Lend_\@ # returning to user-space with LDT SS + + /* + * Setup and switch to ESPFIX stack + * + * We're returning to userspace with a 16 bit stack. The CPU will not + * restore the high word of ESP for us on executing iret... This is an + * "official" bug of all the x86-compatible CPUs, which we can work + * around to make dosemu and wine happy. We do this by preloading the + * high word of ESP with the high word of the userspace ESP while + * compensating for the offset by changing to the ESPFIX segment with + * a base address that matches for the difference. + */ + mov %esp, %edx /* load kernel esp */ + mov PT_OLDESP(%esp), %eax /* load userspace esp */ + mov %dx, %ax /* eax: new kernel esp */ + sub %eax, %edx /* offset (low word is 0) */ + shr $16, %edx + mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */ + mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */ + pushl $__ESPFIX_SS + pushl %eax /* new kernel esp */ + /* + * Disable interrupts, but do not irqtrace this section: we + * will soon execute iret and the tracer was already set to + * the irqstate after the IRET: + */ + DISABLE_INTERRUPTS(CLBR_ANY) + lss (%esp), %esp /* switch to espfix segment */ +.Lend_\@: +#endif /* CONFIG_X86_ESPFIX32 */ +.endm /* * %eax: prev task * %edx: next task @@ -547,21 +595,7 @@ ENTRY(entry_INT80_32) restore_all: TRACE_IRQS_IRET .Lrestore_all_notrace: -#ifdef CONFIG_X86_ESPFIX32 - ALTERNATIVE "jmp .Lrestore_nocheck", "", X86_BUG_ESPFIX - - movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS - /* - * Warning: PT_OLDSS(%esp) contains the wrong/random values if we - * are returning to the kernel. - * See comments in process.c:copy_thread() for details. - */ - movb PT_OLDSS(%esp), %ah - movb PT_CS(%esp), %al - andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax - cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax - je .Lldt_ss # returning to user-space with LDT SS -#endif + CHECK_AND_APPLY_ESPFIX .Lrestore_nocheck: RESTORE_REGS 4 # skip orig_eax/error_code .Lirq_return: @@ -579,39 +613,6 @@ ENTRY(iret_exc ) jmp common_exception .previous _ASM_EXTABLE(.Lirq_return, iret_exc) - -#ifdef CONFIG_X86_ESPFIX32 -.Lldt_ss: -/* - * Setup and switch to ESPFIX stack - * - * We're returning to userspace with a 16 bit stack. The CPU will not - * restore the high word of ESP for us on executing iret... This is an - * "official" bug of all the x86-compatible CPUs, which we can work - * around to make dosemu and wine happy. We do this by preloading the - * high word of ESP with the high word of the userspace ESP while - * compensating for the offset by changing to the ESPFIX segment with - * a base address that matches for the difference. - */ -#define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8) - mov %esp, %edx /* load kernel esp */ - mov PT_OLDESP(%esp), %eax /* load userspace esp */ - mov %dx, %ax /* eax: new kernel esp */ - sub %eax, %edx /* offset (low word is 0) */ - shr $16, %edx - mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */ - mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */ - pushl $__ESPFIX_SS - pushl %eax /* new kernel esp */ - /* - * Disable interrupts, but do not irqtrace this section: we - * will soon execute iret and the tracer was already set to - * the irqstate after the IRET: - */ - DISABLE_INTERRUPTS(CLBR_ANY) - lss (%esp), %esp /* switch to espfix segment */ - jmp .Lrestore_nocheck -#endif ENDPROC(entry_INT80_32) .macro FIXUP_ESPFIX_STACK