From patchwork Thu Oct 29 19:25:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Konovalov X-Patchwork-Id: 11867183 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF5C4697 for ; Thu, 29 Oct 2020 19:26:23 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 9AC0A2083B for ; Thu, 29 Oct 2020 19:26:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=google.com header.i=@google.com header.b="qO3xF8jJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9AC0A2083B Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 758446B0075; Thu, 29 Oct 2020 15:26:22 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 6DFC96B0078; Thu, 29 Oct 2020 15:26:22 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 5801B6B007B; Thu, 29 Oct 2020 15:26:22 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0235.hostedemail.com [216.40.44.235]) by kanga.kvack.org (Postfix) with ESMTP id 24D726B0075 for ; Thu, 29 Oct 2020 15:26:22 -0400 (EDT) Received: from smtpin05.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay02.hostedemail.com (Postfix) with ESMTP id BD1873628 for ; Thu, 29 Oct 2020 19:26:21 +0000 (UTC) X-FDA: 77425944162.05.key39_300be9b2728f Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin05.hostedemail.com (Postfix) with ESMTP id 98ABD180279B1 for ; Thu, 29 Oct 2020 19:26:21 +0000 (UTC) X-Spam-Summary: 1,0,0,568dda00b9962f3a,d41d8cd98f00b204,3whebxwokcpczmcqdxjmukfnnfkd.bnlkhmtw-lljuzbj.nqf@flex--andreyknvl.bounces.google.com,,RULES_HIT:41:152:355:379:541:800:960:973:988:989:1260:1277:1313:1314:1345:1359:1431:1437:1516:1518:1535:1544:1593:1594:1605:1711:1730:1747:1777:1792:2393:2559:2562:2693:3138:3139:3140:3141:3142:3152:3865:3866:3867:3868:3870:3871:3872:4118:4250:4321:4605:5007:6117:6119:6121:6261:6653:6742:7576:7903:9165:9969:10004:11026:11232:11473:11657:11658:11914:12043:12291:12296:12297:12438:12555:12679:12683:12895:12986:13149:13161:13229:13230:14181:14394:14659:14721:14819:21080:21365:21444:21451:21627:21795:21939:21966:21990:30003:30012:30051:30054:30070,0,RBL:209.85.128.74:@flex--andreyknvl.bounces.google.com:.lbl8.mailshell.net-62.18.0.100 66.100.201.100;04yfmib1qftdejywni8heoohu6zyxocudxf8cfb1n6o95136mjwycd5uhxqcxtd.39zawdsh5s8dof8mgzzjgy5oe9tui3ojggiqxsertyiffyk4heb7omppojzg64g.6-lbl8.mailshell.net-223.238.255.100,CacheIP:none,Bayesian:0.5,0.5 ,0.5,Net X-HE-Tag: key39_300be9b2728f X-Filterd-Recvd-Size: 7512 Received: from mail-wm1-f74.google.com (mail-wm1-f74.google.com [209.85.128.74]) by imf19.hostedemail.com (Postfix) with ESMTP for ; Thu, 29 Oct 2020 19:26:21 +0000 (UTC) Received: by mail-wm1-f74.google.com with SMTP id z62so972427wmb.1 for ; Thu, 29 Oct 2020 12:26:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=Xhi8/obcRMlNP7+SSdhpfrVDPTS3W5bEgvNhWzgL4po=; b=qO3xF8jJww6KEIMtDNtASxFtQY6Y2DemOe98A76dQ3JxiTYky3BF1ewT+AeRU62WJ8 KF9f6hD8uvlAgUsiH6ajiUP8ompPRpLL5kvZnOHpKPrL96ZG8fDmlFrq3SsqzmvyBybp CQVzHu6zplWxborIQSb+haHta6aJ5RNtqvqVtf6ETFaGrrN9GufZTHyivMXBOcVjfIGr 2JZZjdKBM6FgrcloZBy0gkux7qZBf7xNeP9K71nzLkSb+1OD/YPp5C7FKaHCAbVxOda9 6jDMgc9D2yzqLfD/beknbaRPKGJ/IMzjhCkXSdkdddKV/7HcRqsodc7EPiaxWlhcctCW TSpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=Xhi8/obcRMlNP7+SSdhpfrVDPTS3W5bEgvNhWzgL4po=; b=Pk9L14XJWhv6tiw9wH/JKBRTbAGdljkh+/jx5Plh4MoRFowp6VxNqoKaucmPU5u6Ge 4fGbsDZJopwh1PW0ieoAl58/waziOyJ0tVqloBIs4NqLiol1Eb/SYr0lj8SoNe27G7TN bapmwI7QCacUbvcPkExFsIls8PHuyNomAEHP8L1YSz82xTKVFuYHvLMFpQVDurazifZA EJ15hATfVf5O7a8hcxGwYR8Ae9Vn+7f8IfvylXuyWHDsKMwZxBZXI8LY/vJOs6cGewJk G5ma/Fs6hX9gsf2E8ZTK3KLaqGw5OYBvSvK/KWbsZqimWPVydKn1yf+7rW3qJAFQ2V+w H9CA== X-Gm-Message-State: AOAM5323f8Xg5sMcY0tvjH+kj2XJlxpeSPlCb1AeXbCgE5xRayk/tbdY v+dGVBU4ucUhlyqJxhIAhSGDt0DCdDxuGv/O X-Google-Smtp-Source: ABdhPJyTlbJXIhbjP/sFdUUSRHNn8GDikF4/IbwVZuWnl/plqIXe5pLu/Tc/r0CDeozv5WgyXwzBwLbxVKmbmVc1 X-Received: from andreyknvl3.muc.corp.google.com ([2a00:79e0:15:13:7220:84ff:fe09:7e9d]) (user=andreyknvl job=sendgmr) by 2002:a7b:c149:: with SMTP id z9mr50488wmi.0.1603999578948; Thu, 29 Oct 2020 12:26:18 -0700 (PDT) Date: Thu, 29 Oct 2020 20:25:26 +0100 In-Reply-To: Message-Id: <171f9481fe4d116c46cc25a4b1145622ee62440e.1603999489.git.andreyknvl@google.com> Mime-Version: 1.0 References: X-Mailer: git-send-email 2.29.1.341.ge80a0c044ae-goog Subject: [PATCH v6 05/40] arm64: mte: Add in-kernel tag fault handler From: Andrey Konovalov To: Catalin Marinas , Will Deacon Cc: Vincenzo Frascino , kasan-dev@googlegroups.com, Dmitry Vyukov , Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Elena Petrova , Branislav Rankov , Kevin Brodsky , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrey Konovalov X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Vincenzo Frascino Add the implementation of the in-kernel fault handler. When a tag fault happens on a kernel address: * MTE is disabled on the current CPU, * the execution continues. When a tag fault happens on a user address: * the kernel executes do_bad_area() and panics. The tag fault handler for kernel addresses is currently empty and will be filled in by a future commit. Signed-off-by: Vincenzo Frascino Co-developed-by: Andrey Konovalov Signed-off-by: Andrey Konovalov --- Change-Id: I9b8aa79567f7c45f4d6a1290efcf34567e620717 --- arch/arm64/include/asm/uaccess.h | 23 ++++++++++++++++ arch/arm64/mm/fault.c | 45 ++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 991dd5f031e4..c7fff8daf2a7 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -200,13 +200,36 @@ do { \ CONFIG_ARM64_PAN)); \ } while (0) +/* + * The Tag Check Flag (TCF) mode for MTE is per EL, hence TCF0 + * affects EL0 and TCF affects EL1 irrespective of which TTBR is + * used. + * The kernel accesses TTBR0 usually with LDTR/STTR instructions + * when UAO is available, so these would act as EL0 accesses using + * TCF0. + * However futex.h code uses exclusives which would be executed as + * EL1, this can potentially cause a tag check fault even if the + * user disables TCF0. + * + * To address the problem we set the PSTATE.TCO bit in uaccess_enable() + * and reset it in uaccess_disable(). + * + * The Tag check override (TCO) bit disables temporarily the tag checking + * preventing the issue. + */ static inline void uaccess_disable(void) { + asm volatile(ALTERNATIVE("nop", SET_PSTATE_TCO(0), + ARM64_MTE, CONFIG_KASAN_HW_TAGS)); + __uaccess_disable(ARM64_HAS_PAN); } static inline void uaccess_enable(void) { + asm volatile(ALTERNATIVE("nop", SET_PSTATE_TCO(1), + ARM64_MTE, CONFIG_KASAN_HW_TAGS)); + __uaccess_enable(ARM64_HAS_PAN); } diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 94c99c1c19e3..7be8f3f64285 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -296,6 +297,44 @@ static void die_kernel_fault(const char *msg, unsigned long addr, do_exit(SIGKILL); } +static void report_tag_fault(unsigned long addr, unsigned int esr, + struct pt_regs *regs) +{ +} + +static void do_tag_recovery(unsigned long addr, unsigned int esr, + struct pt_regs *regs) +{ + static bool reported = false; + + if (!READ_ONCE(reported)) { + report_tag_fault(addr, esr, regs); + WRITE_ONCE(reported, true); + } + + /* + * Disable MTE Tag Checking on the local CPU for the current EL. + * It will be done lazily on the other CPUs when they will hit a + * tag fault. + */ + sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_NONE); + isb(); +} + +static bool is_el1_mte_sync_tag_check_fault(unsigned int esr) +{ + unsigned int ec = ESR_ELx_EC(esr); + unsigned int fsc = esr & ESR_ELx_FSC; + + if (ec != ESR_ELx_EC_DABT_CUR) + return false; + + if (fsc == ESR_ELx_FSC_MTE) + return true; + + return false; +} + static void __do_kernel_fault(unsigned long addr, unsigned int esr, struct pt_regs *regs) { @@ -312,6 +351,12 @@ static void __do_kernel_fault(unsigned long addr, unsigned int esr, "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr)) return; + if (is_el1_mte_sync_tag_check_fault(esr)) { + do_tag_recovery(addr, esr, regs); + + return; + } + if (is_el1_permission_fault(addr, esr, regs)) { if (esr & ESR_ELx_WNR) msg = "write to read-only memory";