From patchwork Mon Nov 19 21:49:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-cheng Yu X-Patchwork-Id: 10689589 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E395C13BB for ; Mon, 19 Nov 2018 21:56:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D4AB52A583 for ; Mon, 19 Nov 2018 21:56:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C8C312A6EE; Mon, 19 Nov 2018 21:56:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 34F6B2A583 for ; Mon, 19 Nov 2018 21:56:04 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 2FBE66B1CBB; Mon, 19 Nov 2018 16:55:08 -0500 (EST) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 25BB66B1CBC; Mon, 19 Nov 2018 16:55:08 -0500 (EST) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 100B16B1CBD; Mon, 19 Nov 2018 16:55:07 -0500 (EST) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by kanga.kvack.org (Postfix) with ESMTP id AE6096B1CBB for ; Mon, 19 Nov 2018 16:55:07 -0500 (EST) Received: by mail-pl1-f198.google.com with SMTP id h10so6902992plk.12 for ; Mon, 19 Nov 2018 13:55:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-original-authentication-results:x-gm-message-state:from:to:cc :subject:date:message-id:in-reply-to:references; bh=zu5NeJf5RMqlUWUdu0IGKhL8xoton6ubAdximKz6P48=; b=JJwfjw6C7HbJOEy32r7c1CMYGOrgmJDvgenG1MIFxJT30Z9ypAeU569ZL0I8jkWiHo 49cQw6SkYWbW8uC4zijS7XGu+mVHGdWJdDvVvM5iKl+TEDAHFk8lQlete8CHb/VI2yz/ eujmnkKYV6Kbh+Xm1YOSS4mn3+8f+nXP4TVHY5kUVJmLSlwi7rAPUjedJNN6L//Hha09 UCz2d7KoWFgVNkdqosf/5ERN1fFHVaLt3z10DIf0jW4hcjy5GcPMrX56NfG6p7j38OF8 xv9tbuPcm8otPQJglfDXyfchTM4ypXatkYLU3T997x9Dn2sn18oZ3uJqryvcM8c4DXB+ 35ww== X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of yu-cheng.yu@intel.com designates 192.55.52.93 as permitted sender) smtp.mailfrom=yu-cheng.yu@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Gm-Message-State: AGRZ1gJTi/9nSmZXXv3UIERzsOTHwz/Q0uClFvupDZP+A0qOItdS2exn nKde4SEfHzFsQZgDAa8RcnyxSwOS/0glCNxTLn2oWmEw9Ls3tPwRkTz74m9T/JSIXtiaaLJWN2Y xHgNXSD7Av4/rn+/BigkKMdDvU2/muUs//sK0LmjpPD+lyeCjI3XmFHyTcCJ2kh3rCg== X-Received: by 2002:a62:e044:: with SMTP id f65mr24700972pfh.208.1542664507386; Mon, 19 Nov 2018 13:55:07 -0800 (PST) X-Google-Smtp-Source: AJdET5dKbnMaM1SZYcZI9KKKYrXk2UixxGWKjHmQhh0HpHkiGkmjNbK4PigIJDGOWJ09MNg0SqbC X-Received: by 2002:a62:e044:: with SMTP id f65mr24700930pfh.208.1542664506640; Mon, 19 Nov 2018 13:55:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542664506; cv=none; d=google.com; s=arc-20160816; b=bWFLTQavAlBHFcesWW0VBWLhPVLWz9x5RLrpdG/osiNbbJrafPF6OX5BORF8QU8uKO 2bSIOa266EfwpT/8bFuHqhlBl/p6T2pjFOML2x/3Jh/rEIC4h1aa3KSkdBElNoCsj921 1q4D/rzBYO1nNbCy8+6/WDtIEG2QDd0CqmCeX5G+r2IOBUvUntJbgQwnjczQubCsfB7t gRKjF7PpYmMU1zqk1mhOllg58W+N5yHIcpMWNJtuoyKnYTZP4eXF8YGcx/KKZCqVAsyd iUwTjsMSUdt2f6E6AD7ml7DJ/s2hcW8/JSSx9l4zqSz0JzvIajCB8nH1b+tXybAVD5eF RAWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from; bh=zu5NeJf5RMqlUWUdu0IGKhL8xoton6ubAdximKz6P48=; b=QUeMNQp5MwXjs+2tRQwj9r7Z7I7wyLX0oAbyrMO/pr+ymSgW3CGUOGXyqx67kS+4mL 727o1gA6x/MuTFLlah+wtSRbLOi1VADttOCavu+wX4IcEZDkVqfpVMHr8VQDUwo0Dkfz rg76sYx4pWpV+I5Mo99pNXe6Ni3eEI+Ti+Ir5i3H25IMOpcTznSt/LV4yfBHUsAQ+TWH On3tNQLZgr5Op6wULPKEwwFupS6q93YB9FePjpdWCiQM/OZZU2gHUEbc9aulvyVDQOla imAXPZ4Nl3605uZ4LaVANhLpe92r69BDt//SEnxNLyzhXgdbT3QpVf4Hk/wmJyaZe/Fx G8DA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of yu-cheng.yu@intel.com designates 192.55.52.93 as permitted sender) smtp.mailfrom=yu-cheng.yu@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from mga11.intel.com (mga11.intel.com. [192.55.52.93]) by mx.google.com with ESMTPS id s8si4586261plq.345.2018.11.19.13.55.06 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 19 Nov 2018 13:55:06 -0800 (PST) Received-SPF: pass (google.com: domain of yu-cheng.yu@intel.com designates 192.55.52.93 as permitted sender) client-ip=192.55.52.93; Authentication-Results: mx.google.com; spf=pass (google.com: domain of yu-cheng.yu@intel.com designates 192.55.52.93 as permitted sender) smtp.mailfrom=yu-cheng.yu@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Nov 2018 13:55:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,254,1539673200"; d="scan'208";a="92423937" Received: from yyu32-desk1.sc.intel.com ([143.183.136.147]) by orsmga006.jf.intel.com with ESMTP; 19 Nov 2018 13:55:05 -0800 From: Yu-cheng Yu To: x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue Cc: Yu-cheng Yu Subject: [RFC PATCH v6 11/11] x86/cet: Add PTRACE interface for CET Date: Mon, 19 Nov 2018 13:49:34 -0800 Message-Id: <20181119214934.6174-12-yu-cheng.yu@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181119214934.6174-1-yu-cheng.yu@intel.com> References: <20181119214934.6174-1-yu-cheng.yu@intel.com> X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP Add REGSET_CET64/REGSET_CET32 to get/set CET MSRs: IA32_U_CET (user-mode CET settings) and IA32_PL3_SSP (user-mode shadow stack) Signed-off-by: Yu-cheng Yu --- arch/x86/include/asm/fpu/regset.h | 7 +++--- arch/x86/kernel/fpu/regset.c | 41 +++++++++++++++++++++++++++++++ arch/x86/kernel/ptrace.c | 16 ++++++++++++ include/uapi/linux/elf.h | 1 + 4 files changed, 62 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/fpu/regset.h b/arch/x86/include/asm/fpu/regset.h index d5bdffb9d27f..edad0d889084 100644 --- a/arch/x86/include/asm/fpu/regset.h +++ b/arch/x86/include/asm/fpu/regset.h @@ -7,11 +7,12 @@ #include -extern user_regset_active_fn regset_fpregs_active, regset_xregset_fpregs_active; +extern user_regset_active_fn regset_fpregs_active, regset_xregset_fpregs_active, + cetregs_active; extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get, - xstateregs_get; + xstateregs_get, cetregs_get; extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set, - xstateregs_set; + xstateregs_set, cetregs_set; /* * xstateregs_active == regset_fpregs_active. Please refer to the comment diff --git a/arch/x86/kernel/fpu/regset.c b/arch/x86/kernel/fpu/regset.c index bc02f5144b95..7008eb084d36 100644 --- a/arch/x86/kernel/fpu/regset.c +++ b/arch/x86/kernel/fpu/regset.c @@ -160,6 +160,47 @@ int xstateregs_set(struct task_struct *target, const struct user_regset *regset, return ret; } +int cetregs_active(struct task_struct *target, const struct user_regset *regset) +{ +#ifdef CONFIG_X86_INTEL_CET + if (target->thread.cet.shstk_enabled || target->thread.cet.ibt_enabled) + return regset->n; +#endif + return 0; +} + +int cetregs_get(struct task_struct *target, const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + struct fpu *fpu = &target->thread.fpu; + struct cet_user_state *cetregs; + + if (!boot_cpu_has(X86_FEATURE_SHSTK)) + return -ENODEV; + + cetregs = get_xsave_addr(&fpu->state.xsave, XFEATURE_MASK_SHSTK_USER); + + fpu__prepare_read(fpu); + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, cetregs, 0, -1); +} + +int cetregs_set(struct task_struct *target, const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct fpu *fpu = &target->thread.fpu; + struct cet_user_state *cetregs; + + if (!boot_cpu_has(X86_FEATURE_SHSTK)) + return -ENODEV; + + cetregs = get_xsave_addr(&fpu->state.xsave, XFEATURE_MASK_SHSTK_USER); + + fpu__prepare_write(fpu); + return user_regset_copyin(&pos, &count, &kbuf, &ubuf, cetregs, 0, -1); +} + #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION /* diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c index ffae9b9740fd..780b350577bc 100644 --- a/arch/x86/kernel/ptrace.c +++ b/arch/x86/kernel/ptrace.c @@ -50,7 +50,9 @@ enum x86_regset { REGSET_IOPERM64 = REGSET_XFP, REGSET_XSTATE, REGSET_TLS, + REGSET_CET64 = REGSET_TLS, REGSET_IOPERM32, + REGSET_CET32, }; struct pt_regs_offset { @@ -1266,6 +1268,13 @@ static struct user_regset x86_64_regsets[] __ro_after_init = { .size = sizeof(long), .align = sizeof(long), .active = ioperm_active, .get = ioperm_get }, + [REGSET_CET64] = { + .core_note_type = NT_X86_CET, + .n = sizeof(struct cet_user_state) / sizeof(u64), + .size = sizeof(u64), .align = sizeof(u64), + .active = cetregs_active, .get = cetregs_get, + .set = cetregs_set + }, }; static const struct user_regset_view user_x86_64_view = { @@ -1321,6 +1330,13 @@ static struct user_regset x86_32_regsets[] __ro_after_init = { .size = sizeof(u32), .align = sizeof(u32), .active = ioperm_active, .get = ioperm_get }, + [REGSET_CET32] = { + .core_note_type = NT_X86_CET, + .n = sizeof(struct cet_user_state) / sizeof(u64), + .size = sizeof(u64), .align = sizeof(u64), + .active = cetregs_active, .get = cetregs_get, + .set = cetregs_set + }, }; static const struct user_regset_view user_x86_32_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 5ef25a565e88..f4cdfdc59c0a 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -401,6 +401,7 @@ typedef struct elf64_shdr { #define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ #define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */ #define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */ +#define NT_X86_CET 0x203 /* x86 cet state */ #define NT_S390_HIGH_GPRS 0x300 /* s390 upper register halves */ #define NT_S390_TIMER 0x301 /* s390 timer register */ #define NT_S390_TODCMP 0x302 /* s390 TOD clock comparator register */