From patchwork Thu Mar 12 04:10:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenyu Ye X-Patchwork-Id: 11433183 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 08D9992A for ; Thu, 12 Mar 2020 04:10:52 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id AE8F0206FA for ; Thu, 12 Mar 2020 04:10:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AE8F0206FA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 36A536B0008; Thu, 12 Mar 2020 00:10:49 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 31A9F6B000A; Thu, 12 Mar 2020 00:10:49 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 1BA8C6B000D; Thu, 12 Mar 2020 00:10:49 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0216.hostedemail.com [216.40.44.216]) by kanga.kvack.org (Postfix) with ESMTP id E29F86B000C for ; Thu, 12 Mar 2020 00:10:48 -0400 (EDT) Received: from smtpin17.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay03.hostedemail.com (Postfix) with ESMTP id DB4CF8248068 for ; Thu, 12 Mar 2020 04:10:48 +0000 (UTC) X-FDA: 76585384176.17.join78_242316887be1f X-Spam-Summary: 1,0,0,,d41d8cd98f00b204,yezhenyu2@huawei.com,,RULES_HIT:30054:30080,0,RBL:45.249.212.35:@huawei.com:.lbl8.mailshell.net-64.95.201.95 62.18.2.100,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fp,MSBL:0,DNSBL:neutral,Custom_rules:0:0:0,LFtime:23,LUA_SUMMARY:none X-HE-Tag: join78_242316887be1f X-Filterd-Recvd-Size: 4427 Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by imf48.hostedemail.com (Postfix) with ESMTP for ; Thu, 12 Mar 2020 04:10:48 +0000 (UTC) Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id A9DD3C064D0E03BC613E; Thu, 12 Mar 2020 12:10:36 +0800 (CST) Received: from DESKTOP-KKJBAGG.china.huawei.com (10.173.220.25) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.487.0; Thu, 12 Mar 2020 12:10:27 +0800 From: Zhenyu Ye To: , , , , , , , CC: , , , , , , , , Subject: [RFC PATCH v2 2/3] arm64: tlb: use mm_struct.context.flags to indicate TTL value Date: Thu, 12 Mar 2020 12:10:17 +0800 Message-ID: <20200312041018.1927-3-yezhenyu2@huawei.com> X-Mailer: git-send-email 2.22.0.windows.1 In-Reply-To: <20200312041018.1927-1-yezhenyu2@huawei.com> References: <20200312041018.1927-1-yezhenyu2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.220.25] X-CFilter-Loop: Reflected X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Use Architecture-specific MM context to indicate the level of page table walk. This avoids lots of changes to common-interface. Signed-off-by: Zhenyu Ye --- arch/arm64/include/asm/mmu.h | 11 +++++++++++ arch/arm64/include/asm/tlbflush.h | 6 +++--- arch/arm64/kernel/process.c | 2 +- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index e4d862420bb4..f86a38ab3632 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -8,6 +8,10 @@ #include #define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */ +#define S1_PUD_LEVEL 0x10 /* mm context flag for the level of ptw */ +#define S1_PMD_LEVEL 0x20 +#define S1_PTE_LEVEL 0x30 + #define USER_ASID_BIT 48 #define USER_ASID_FLAG (UL(1) << USER_ASID_BIT) #define TTBR_ASID_MASK (UL(0xffff) << 48) @@ -19,6 +23,10 @@ typedef struct { atomic64_t id; void *vdso; + /* + * flags[3:0]: AArch32 executables + * flags[7:4]: the level of page table walk + */ unsigned long flags; } mm_context_t; @@ -29,6 +37,9 @@ typedef struct { */ #define ASID(mm) ((mm)->context.id.counter & 0xffff) +/* This macro is only used by TLBI TTL */ +#define TLBI_LEVEL(mm) ((mm)->context.flags >> 4 & 0xf) + extern bool arm64_use_ng_mappings; static inline bool arm64_kernel_unmapped_at_el0(void) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index dda693f32099..312b9edb281b 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -186,7 +186,7 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); dsb(ishst); - __tlbi_level(vale1is, addr, 0); + __tlbi_level(vale1is, addr, TLBI_LEVEL(vma->vm_mm)); } static inline void flush_tlb_page(struct vm_area_struct *vma, @@ -226,9 +226,9 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, dsb(ishst); for (addr = start; addr < end; addr += stride) { if (last_level) { - __tlbi_level(vale1is, addr, 0); + __tlbi_level(vale1is, addr, TLBI_LEVEL(vma->vm_mm)); } else { - __tlbi_level(vae1is, addr, 0); + __tlbi_level(vae1is, addr, TLBI_LEVEL(vma->vm_mm)); } } dsb(ish); diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index bbb0f0c145f6..bf835755d9ed 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -562,7 +562,7 @@ unsigned long arch_align_stack(unsigned long sp) */ void arch_setup_new_exec(void) { - current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0; + current->mm->context.flags |= is_compat_task() ? MMCF_AARCH32 : 0; ptrauth_thread_init_user(current); }