From patchwork Wed Jul 15 17:08:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 11665989 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A5AB96C1 for ; Wed, 15 Jul 2020 17:09:24 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 746C120672 for ; Wed, 15 Jul 2020 17:09:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 746C120672 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 91EE68D000E; Wed, 15 Jul 2020 13:09:19 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 8A89E8D0002; Wed, 15 Jul 2020 13:09:19 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 74AB88D000E; Wed, 15 Jul 2020 13:09:19 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0182.hostedemail.com [216.40.44.182]) by kanga.kvack.org (Postfix) with ESMTP id 548BD8D0002 for ; Wed, 15 Jul 2020 13:09:19 -0400 (EDT) Received: from smtpin14.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay04.hostedemail.com (Postfix) with ESMTP id 16B2D1EF1 for ; Wed, 15 Jul 2020 17:09:19 +0000 (UTC) X-FDA: 77040946038.14.rock67_2e0789726efb Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin14.hostedemail.com (Postfix) with ESMTP id D2AF21822987A for ; Wed, 15 Jul 2020 17:09:18 +0000 (UTC) X-Spam-Summary: 40,2.5,0,58ec0345a71e1781,d41d8cd98f00b204,cmainas@kernel.org,,RULES_HIT:41:355:379:541:800:960:973:988:989:1260:1311:1314:1345:1359:1437:1515:1534:1543:1711:1730:1747:1777:1792:2194:2198:2199:2200:2393:2553:2559:2562:2693:2731:2895:2903:3138:3139:3140:3141:3142:3354:3865:3866:3867:3868:3870:3871:3874:4250:4321:5007:6119:6261:7903:9592:10011:11026:11232:11473:11657:11658:11914:12043:12297:12438:12517:12519:12555:12986:13149:13161:13180:13229:13230:13894:13972:14181:14394:14721:21080:21230:21433:21451:21627:21740:21966:21990:30012:30034:30054:30055:30070:30090,0,RBL:198.145.29.99:@kernel.org:.lbl8.mailshell.net-62.2.0.100 64.100.201.201;04yrd1fse31qsmecrf4si85drhqz6ycun9orq5pcbexrdyde3douxmehnwwhu4y.mmnckn1igudyoepxhpwdyg91rydb6hix8ebwg67k6knm683b9h1t5uz51z197xx.h-lbl8.mailshell.net-223.238.255.100,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fp,MSBL:0,DNSBL:neutral,Custom_rules:0:1:0,LFtime:22,LUA_SUMMARY:none X-HE-Tag: rock67_2e0789726efb X-Filterd-Recvd-Size: 4530 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by imf48.hostedemail.com (Postfix) with ESMTP for ; Wed, 15 Jul 2020 17:09:18 +0000 (UTC) Received: from localhost.localdomain (unknown [95.146.230.158]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B6711206F4; Wed, 15 Jul 2020 17:09:15 +0000 (UTC) From: Catalin Marinas To: linux-arm-kernel@lists.infradead.org Cc: linux-mm@kvack.org, linux-arch@vger.kernel.org, Will Deacon , Dave P Martin , Vincenzo Frascino , Szabolcs Nagy , Kevin Brodsky , Andrey Konovalov , Peter Collingbourne , Andrew Morton Subject: [PATCH v7 12/29] arm64: mte: Handle the MAIR_EL1 changes for late CPU bring-up Date: Wed, 15 Jul 2020 18:08:27 +0100 Message-Id: <20200715170844.30064-13-catalin.marinas@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200715170844.30064-1-catalin.marinas@arm.com> References: <20200715170844.30064-1-catalin.marinas@arm.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: D2AF21822987A X-Spamd-Result: default: False [0.00 / 100.00] X-Rspamd-Server: rspam01 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: CnP must be enabled only after the MAIR_EL1 register has been set up by the cpu_enable_mte() function. Inconsistent MAIR_EL1 between CPUs sharing the same TLB may lead to the wrong memory type being used for a brief window during CPU power-up. Move the ARM64_HAS_CNP capability to a higher number and add a corresponding BUILD_BUG_ON() to check for any inadvertent future change in the relative positions of MTE and CnP. The cpufeature.c code ensures that the cpu_enable() function is called in the ascending order of the capability number. In addition, move the TLB invalidation to cpu_enable_mte() since late CPUs brought up won't be covered by the flush_tlb_all() in system_enable_mte(). Signed-off-by: Catalin Marinas Cc: Will Deacon --- Notes: New in v7. arch/arm64/include/asm/cpucaps.h | 4 ++-- arch/arm64/kernel/cpufeature.c | 14 ++++++++++---- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 6bc3e21e5929..bc39fdbf0706 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -22,7 +22,7 @@ #define ARM64_WORKAROUND_CAVIUM_27456 12 #define ARM64_HAS_32BIT_EL0 13 #define ARM64_HARDEN_EL2_VECTORS 14 -#define ARM64_HAS_CNP 15 +#define ARM64_MTE 15 #define ARM64_HAS_NO_FPSIMD 16 #define ARM64_WORKAROUND_REPEAT_TLBI 17 #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 @@ -62,7 +62,7 @@ #define ARM64_HAS_GENERIC_AUTH 52 #define ARM64_HAS_32BIT_EL1 53 #define ARM64_BTI 54 -#define ARM64_MTE 55 +#define ARM64_HAS_CNP 55 #define ARM64_NCAPS 56 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c1df72bfede4..4d3abb51f7d4 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1670,6 +1670,14 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) write_sysreg_s(0, SYS_TFSR_EL1); write_sysreg_s(0, SYS_TFSRE0_EL1); + /* + * CnP must be enabled only after the MAIR_EL1 register has been set + * up. Inconsistent MAIR_EL1 between CPUs sharing the same TLB may + * lead to the wrong memory type being used for a brief window during + * CPU power-up. + */ + BUILD_BUG_ON(ARM64_HAS_CNP < ARM64_MTE); + /* * Update the MT_NORMAL_TAGGED index in MAIR_EL1. Tag checking is * disabled for the kernel, so there won't be any observable effect @@ -1679,8 +1687,9 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) mair &= ~MAIR_ATTRIDX(MAIR_ATTR_MASK, MT_NORMAL_TAGGED); mair |= MAIR_ATTRIDX(MAIR_ATTR_NORMAL_TAGGED, MT_NORMAL_TAGGED); write_sysreg_s(mair, SYS_MAIR_EL1); - isb(); + + local_flush_tlb_all(); } static int __init system_enable_mte(void) @@ -1688,9 +1697,6 @@ static int __init system_enable_mte(void) if (!system_supports_mte()) return 0; - /* Ensure the TLB does not have stale MAIR attributes */ - flush_tlb_all(); - /* * Clear the tags in the zero page. This needs to be done via the * linear map which has the Tagged attribute.