From patchwork Thu Jul 23 14:57:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 11681155 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4999C722 for ; Thu, 23 Jul 2020 15:06:54 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 096D420771 for ; Thu, 23 Jul 2020 15:06:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="DTNtyx73" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 096D420771 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 31B076B002D; Thu, 23 Jul 2020 11:06:47 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 2A42E6B002E; Thu, 23 Jul 2020 11:06:47 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 1934E6B002F; Thu, 23 Jul 2020 11:06:47 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0164.hostedemail.com [216.40.44.164]) by kanga.kvack.org (Postfix) with ESMTP id F1AED6B002D for ; Thu, 23 Jul 2020 11:06:46 -0400 (EDT) Received: from smtpin07.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay05.hostedemail.com (Postfix) with ESMTP id 9C1ED181AF5C4 for ; Thu, 23 Jul 2020 15:06:46 +0000 (UTC) X-FDA: 77069667612.07.fly23_251254c26f3f Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin07.hostedemail.com (Postfix) with ESMTP id CBE181803F792 for ; Thu, 23 Jul 2020 15:05:59 +0000 (UTC) X-Spam-Summary: 1,0,0,de5d99007e820fde,d41d8cd98f00b204,jean-philippe@linaro.org,,RULES_HIT:41:355:379:541:800:960:966:973:988:989:1260:1311:1314:1345:1359:1437:1515:1535:1544:1711:1730:1747:1777:1792:2196:2199:2393:2559:2562:2693:3138:3139:3140:3141:3142:3353:3865:3866:3867:3868:3870:3871:3872:4118:4250:4321:4385:5007:6119:6261:6653:6742:7903:7904:8603:10004:11026:11473:11657:11658:11914:12043:12291:12296:12297:12438:12517:12519:12555:12683:12895:13894:14181:14394:14721:21080:21433:21444:21451:21611:21627:21990:30034:30054:30070,0,RBL:209.85.218.67:@linaro.org:.lbl8.mailshell.net-66.100.201.201 62.2.0.100;04y8wf1nh4u8y54i44sriewxikbfuyc5kmn91a1fgjyejrhyz6w4btuwfbjc1kj.wcfxk43q3fwwgcum9b4pe7rbxhw7ecczcyoydinfhqd979hu11fxhmtb6u6jdsf.n-lbl8.mailshell.net-223.238.255.100,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:ft,MSBL:0,DNSBL:neutral,Custom_rules:0:0:0,LFtime:24,LUA_SUMMARY:none X-HE-Tag: fly23_251254c26f3f X-Filterd-Recvd-Size: 7382 Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) by imf31.hostedemail.com (Postfix) with ESMTP for ; Thu, 23 Jul 2020 15:05:58 +0000 (UTC) Received: by mail-ej1-f67.google.com with SMTP id lx13so6750116ejb.4 for ; Thu, 23 Jul 2020 08:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A7i0TfeVtbmivmToJFYuNh5KNdNgY1vTU0jTEZh4S44=; b=DTNtyx73PEuwQyesbHMqyc9KRfKpkQLrDtcn1RgI9i4L3sTyOvObkePC3pFEX6wvt2 MIPUw9T6dRpslzm2jPvmVSks4HcWd+hvazFQVLaoWPm4qT56MkiVBeTrDo0ymJnURpj2 vtenI7sn7dpZj89RA0UTYa8k4TPsuWpYkHVMIPHJig94Dckhm80dkYcfoZaio9agcS3n xLhN7up9sW+t4vIeI5iXyj10DWuVy1aOXj157IP5Zw1Wvms2VzR7c2e//IYe0g83KWLS lL5EaldElZ6lyNR+eS+uTZrqidD/jtYbmwQjF5wEK/8KQOm0TvzjICgChVhbUs29LV1G 0cNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A7i0TfeVtbmivmToJFYuNh5KNdNgY1vTU0jTEZh4S44=; b=fOchM0CjnT/YRea1arjG80hYzPl4As8F9xCz8n3IqNAc2S+oXlYNOCytqn4v/3/F1h H/i9TkEk1mJ5aursUN6rJAURYM31/XtZdCrGfiMlhAKd8zGac8mjRgHf8CPW8yPZXwdn PErH6q8RdizLCo8uCCjLzXy2p+YtH1LoCDXGu6WVlXi6JuCIHIC6eDGhe4TxKFMDrZSe E7dPOb5B7lPpZPNq060bOyLkSTsQoclCdq9GCeEgffpiydvFZykAFNZ48YZT7L/Xrj7G l02W0OYzXIpDblJkpxXdbTk1hN4b2hphOfYVCVPHEQizN9GT28tpEPPbXNc3mnDFvNPg z07Q== X-Gm-Message-State: AOAM530tFHr7pqQynl6saFm+F1o+2CKbLHBsPsiPeU6AJ2p5fEm47i8a 94kEj2BQvcwyDUSN/LfB2jd7xA== X-Google-Smtp-Source: ABdhPJyMNuQc7O5Fnv72xrZh/TQxEiIO6uTWkERHUtAM85C0vk1UvtHsBd9/BzGHJAnoYUE3RVudEw== X-Received: by 2002:a17:906:4e87:: with SMTP id v7mr4736862eju.242.1595516757878; Thu, 23 Jul 2020 08:05:57 -0700 (PDT) Received: from localhost.localdomain ([2001:1715:4e26:a7e0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id k15sm2145952eji.49.2020.07.23.08.05.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 08:05:57 -0700 (PDT) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org Cc: joro@8bytes.org, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, baolu.lu@linux.intel.com, Jonathan.Cameron@huawei.com, jacob.jun.pan@linux.intel.com, zhangfei.gao@linaro.org, xuzaibo@huawei.com, zhengxiang9@huawei.com, fenghua.yu@intel.com, hch@infradead.org, Jean-Philippe Brucker , Suzuki K Poulose Subject: [PATCH v9 10/13] iommu/arm-smmu-v3: Check for SVA features Date: Thu, 23 Jul 2020 16:57:22 +0200 Message-Id: <20200723145724.3014766-11-jean-philippe@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200723145724.3014766-1-jean-philippe@linaro.org> References: <20200723145724.3014766-1-jean-philippe@linaro.org> MIME-Version: 1.0 X-Rspamd-Queue-Id: CBE181803F792 X-Spamd-Result: default: False [0.00 / 100.00] X-Rspamd-Server: rspam05 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Aggregate all sanity-checks for sharing CPU page tables with the SMMU under a single ARM_SMMU_FEAT_SVA bit. For PCIe SVA, users also need to check FEAT_ATS and FEAT_PRI. For platform SVA, they will have to check FEAT_STALLS. Introduce ARM_SMMU_FEAT_BTM (Broadcast TLB Maintenance), but don't enable it at the moment. Since the entire VMID space is shared with the CPU, enabling DVM (by clearing SMMU_CR2.PTM) could result in over-invalidation and affect performance of stage-2 mappings. Cc: Suzuki K Poulose Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.h | 10 ++++++++ drivers/iommu/arm-smmu-v3-sva.c | 43 +++++++++++++++++++++++++++++++++ drivers/iommu/arm-smmu-v3.c | 3 +++ 3 files changed, 56 insertions(+) diff --git a/drivers/iommu/arm-smmu-v3.h b/drivers/iommu/arm-smmu-v3.h index 90c08f156b43..7b14b48a26c7 100644 --- a/drivers/iommu/arm-smmu-v3.h +++ b/drivers/iommu/arm-smmu-v3.h @@ -602,6 +602,8 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_STALL_FORCE (1 << 13) #define ARM_SMMU_FEAT_VAX (1 << 14) #define ARM_SMMU_FEAT_RANGE_INV (1 << 15) +#define ARM_SMMU_FEAT_BTM (1 << 16) +#define ARM_SMMU_FEAT_SVA (1 << 17) u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) @@ -683,4 +685,12 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid); bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd); +#ifdef CONFIG_ARM_SMMU_V3_SVA +bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); +#else /* CONFIG_ARM_SMMU_V3_SVA */ +static inline bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) +{ + return false; +} +#endif /* CONFIG_ARM_SMMU_V3_SVA */ #endif /* _ARM_SMMU_V3_H */ diff --git a/drivers/iommu/arm-smmu-v3-sva.c b/drivers/iommu/arm-smmu-v3-sva.c index d590c864bdf3..eedc6c8264f1 100644 --- a/drivers/iommu/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm-smmu-v3-sva.c @@ -153,3 +153,46 @@ static void arm_smmu_free_shared_cd(struct arm_smmu_ctx_desc *cd) kfree(cd); } } + +bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) +{ + unsigned long reg, fld; + unsigned long oas; + unsigned long asid_bits; + + u32 feat_mask = ARM_SMMU_FEAT_BTM | ARM_SMMU_FEAT_COHERENCY; + + if ((smmu->features & feat_mask) != feat_mask) + return false; + + if (!(smmu->pgsize_bitmap & PAGE_SIZE)) + return false; + + /* + * Get the smallest PA size of all CPUs (sanitized by cpufeature). We're + * not even pretending to support AArch32 here. Abort if the MMU outputs + * addresses larger than what we support. + */ + reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_PARANGE_SHIFT); + oas = id_aa64mmfr0_parange_to_phys_shift(fld); + if (smmu->oas < oas) + return false; + + /* We can support bigger ASIDs than the CPU, but not smaller */ + fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_ASID_SHIFT); + asid_bits = fld ? 16 : 8; + if (smmu->asid_bits < asid_bits) + return false; + + /* + * See max_pinned_asids in arch/arm64/mm/context.c. The following is + * generally the maximum number of bindable processes. + */ + if (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) + asid_bits--; + dev_dbg(smmu->dev, "%d shared contexts\n", (1 << asid_bits) - + num_possible_cpus() - 2); + + return true; +} diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 4a47b977ed01..558973e3cc1b 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -3258,6 +3258,9 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) smmu->ias = max(smmu->ias, smmu->oas); + if (arm_smmu_sva_supported(smmu)) + smmu->features |= ARM_SMMU_FEAT_SVA; + dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", smmu->ias, smmu->oas, smmu->features); return 0;