| Message ID | 20210602140416.23573-6-brijesh.singh@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add AMD Secure Nested Paging (SEV-SNP) Guest Support | expand |
On Wed, Jun 02, 2021 at 09:03:59AM -0500, Brijesh Singh wrote: > diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c > index 70f181f20d92..94957c5bdb51 100644 > --- a/arch/x86/kernel/sev-shared.c > +++ b/arch/x86/kernel/sev-shared.c I'm guessing this is in sev-shared.c because it is going to be used by both stages? > @@ -20,6 +20,7 @@ > * out when the .bss section is later cleared. > */ > static u16 ghcb_version __section(".data"); State what this is: /* Bitmap of SEV features supported by the hypervisor */ > +static u64 hv_features __section(".data"); Also, I'm assuming that bitmap remains immutable during the guest lifetime so you can do: static u64 hv_features __ro_after_init; instead, which will do: static u64 hv_features __attribute__((__section__(".data..ro_after_init"))); and it'll be in the data section and then also marked read-only after init, after mark_rodata_ro() more specifically. Thx.
On 6/7/21 9:19 AM, Borislav Petkov wrote: > On Wed, Jun 02, 2021 at 09:03:59AM -0500, Brijesh Singh wrote: >> diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c >> index 70f181f20d92..94957c5bdb51 100644 >> --- a/arch/x86/kernel/sev-shared.c >> +++ b/arch/x86/kernel/sev-shared.c > I'm guessing this is in sev-shared.c because it is going to be used by > both stages? Yes, the function is used by both the stages. >> @@ -20,6 +20,7 @@ >> * out when the .bss section is later cleared. >> */ >> static u16 ghcb_version __section(".data"); > State what this is: > > /* Bitmap of SEV features supported by the hypervisor */ Noted. > >> +static u64 hv_features __section(".data"); > Also, I'm assuming that bitmap remains immutable during the guest > lifetime so you can do: > > static u64 hv_features __ro_after_init; > > instead, which will do: > > static u64 hv_features __attribute__((__section__(".data..ro_after_init"))); > > and it'll be in the data section and then also marked read-only after > init, after mark_rodata_ro() more specifically. Yes, it should be immutable. I will set the ro_after_init section to mark it read-only. thanks
diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index f1e2aacb0d61..981fff2257b9 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -45,6 +45,15 @@ (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) +/* GHCB Hypervisor Feature Request */ +#define GHCB_MSR_HV_FT_REQ 0x080 +#define GHCB_MSR_HV_FT_RESP 0x081 +#define GHCB_MSR_HV_FT_POS 12 +#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) + +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ + (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 7ec91b1359df..134a7c9d91b6 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -13,7 +13,7 @@ #include <asm/sev-common.h> #define GHCB_PROTOCOL_MIN 1ULL -#define GHCB_PROTOCOL_MAX 1ULL +#define GHCB_PROTOCOL_MAX 2ULL #define GHCB_DEFAULT_USAGE 0ULL #define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); } diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 70f181f20d92..94957c5bdb51 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -20,6 +20,7 @@ * out when the .bss section is later cleared. */ static u16 ghcb_version __section(".data"); +static u64 hv_features __section(".data"); static bool __init sev_es_check_cpu_features(void) { @@ -49,6 +50,22 @@ static void __noreturn sev_es_terminate(unsigned int set, unsigned int reason) asm volatile("hlt\n" : : : "memory"); } +static bool get_hv_features(void) +{ + u64 val; + + sev_es_wr_ghcb_msr(GHCB_MSR_HV_FT_REQ); + VMGEXIT(); + + val = sev_es_rd_ghcb_msr(); + if (GHCB_RESP_CODE(val) != GHCB_MSR_HV_FT_RESP) + return false; + + hv_features = GHCB_MSR_HV_FT_RESP_VAL(val); + + return true; +} + static bool sev_es_negotiate_protocol(void) { u64 val; @@ -67,6 +84,10 @@ static bool sev_es_negotiate_protocol(void) ghcb_version = min_t(size_t, GHCB_MSR_PROTO_MAX(val), GHCB_PROTOCOL_MAX); + /* The hypervisor features are available from version 2 onward. */ + if ((ghcb_version >= 2) && !get_hv_features()) + return false; + return true; }
Version 2 of GHCB specification introduced advertisement of a features that are supported by the hypervisor. Define the GHCB MSR protocol and NAE for the hypervisor feature request and query the feature during the GHCB protocol negotitation. See the GHCB specification for more details. Version 2 of GHCB specification adds several new NAEs, most of them are optional except the hypervisor feature. Now that hypervisor feature NAE is implemented, so bump the GHCB maximum support protocol version. Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> --- arch/x86/include/asm/sev-common.h | 9 +++++++++ arch/x86/include/asm/sev.h | 2 +- arch/x86/kernel/sev-shared.c | 21 +++++++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-)