Message ID | 20210820155918.7518-8-brijesh.singh@amd.com (mailing list archive) |
---|---|
State | New |
Headers | show
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Peter Anvin" <hpa@zytor.com>, Ard Biesheuvel <ardb@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>, Sean Christopherson <seanjc@google.com>, Vitaly Kuznetsov <vkuznets@redhat.com>, Wanpeng Li <wanpengli@tencent.com>, Jim Mattson <jmattson@google.com>, Andy Lutomirski <luto@kernel.org>, Dave Hansen <dave.hansen@linux.intel.com>, Sergio Lopez <slp@redhat.com>, Peter Gonda <pgonda@google.com>, Peter Zijlstra <peterz@infradead.org>, Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>, David Rientjes <rientjes@google.com>, Dov Murik <dovmurik@linux.ibm.com>, Tobin Feldman-Fitzthum <tobin@ibm.com>, Borislav Petkov <bp@alien8.de>, Michael Roth <michael.roth@amd.com>, Vlastimil Babka <vbabka@suse.cz>, "Kirill A . Shutemov" <kirill@shutemov.name>, Andi Kleen <ak@linux.intel.com>, tony.luck@intel.com, marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com, Brijesh Singh <brijesh.singh@amd.com> Subject: [PATCH Part2 v5 07/45] x86/traps: Define RMP violation #PF error code Date: Fri, 20 Aug 2021 10:58:40 -0500 Message-Id: <20210820155918.7518-8-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210820155918.7518-1-brijesh.singh@amd.com> References: <20210820155918.7518-1-brijesh.singh@amd.com> Content-Type: text/plain X-ClientProxiedBy: SN7P222CA0013.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::11) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN7P222CA0013.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4436.18 via Frontend Transport; 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Add AMD Secure Nested Paging (SEV-SNP) Hypervisor Support
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expand
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On Fri, Aug 20, 2021 at 10:58:40AM -0500, Brijesh Singh wrote: > enum x86_pf_error_code { > - X86_PF_PROT = 1 << 0, > - X86_PF_WRITE = 1 << 1, > - X86_PF_USER = 1 << 2, > - X86_PF_RSVD = 1 << 3, > - X86_PF_INSTR = 1 << 4, > - X86_PF_PK = 1 << 5, > - X86_PF_SGX = 1 << 15, > + X86_PF_PROT = BIT_ULL(0), > + X86_PF_WRITE = BIT_ULL(1), > + X86_PF_USER = BIT_ULL(2), > + X86_PF_RSVD = BIT_ULL(3), > + X86_PF_INSTR = BIT_ULL(4), > + X86_PF_PK = BIT_ULL(5), > + X86_PF_SGX = BIT_ULL(15), > + X86_PF_RMP = BIT_ULL(31), Those are tested against error_code mostly, which is unsigned long so it looks like you wanna use _BITUL() here. Not that it matters on x86-64 but if we want to be precise...
diff --git a/arch/x86/include/asm/trap_pf.h b/arch/x86/include/asm/trap_pf.h index 10b1de500ab1..89b705114b3f 100644 --- a/arch/x86/include/asm/trap_pf.h +++ b/arch/x86/include/asm/trap_pf.h @@ -2,6 +2,8 @@ #ifndef _ASM_X86_TRAP_PF_H #define _ASM_X86_TRAP_PF_H +#include <linux/bits.h> /* BIT() macro */ + /* * Page fault error code bits: * @@ -12,15 +14,17 @@ * bit 4 == 1: fault was an instruction fetch * bit 5 == 1: protection keys block access * bit 15 == 1: SGX MMU page-fault + * bit 31 == 1: fault was due to RMP violation */ enum x86_pf_error_code { - X86_PF_PROT = 1 << 0, - X86_PF_WRITE = 1 << 1, - X86_PF_USER = 1 << 2, - X86_PF_RSVD = 1 << 3, - X86_PF_INSTR = 1 << 4, - X86_PF_PK = 1 << 5, - X86_PF_SGX = 1 << 15, + X86_PF_PROT = BIT_ULL(0), + X86_PF_WRITE = BIT_ULL(1), + X86_PF_USER = BIT_ULL(2), + X86_PF_RSVD = BIT_ULL(3), + X86_PF_INSTR = BIT_ULL(4), + X86_PF_PK = BIT_ULL(5), + X86_PF_SGX = BIT_ULL(15), + X86_PF_RMP = BIT_ULL(31), }; #endif /* _ASM_X86_TRAP_PF_H */ diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index b2eefdefc108..8b7a5757440e 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -545,6 +545,7 @@ show_fault_oops(struct pt_regs *regs, unsigned long error_code, unsigned long ad !(error_code & X86_PF_PROT) ? "not-present page" : (error_code & X86_PF_RSVD) ? "reserved bit violation" : (error_code & X86_PF_PK) ? "protection keys violation" : + (error_code & X86_PF_RMP) ? "RMP violation" : "permissions violation"); if (!(error_code & X86_PF_USER) && user_mode(regs)) {
Bit 31 in the page fault-error bit will be set when processor encounters an RMP violation. While at it, use the BIT_ULL() macro. Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> --- arch/x86/include/asm/trap_pf.h | 18 +++++++++++------- arch/x86/mm/fault.c | 1 + 2 files changed, 12 insertions(+), 7 deletions(-)