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David Alan Gilbert" , , , , Brijesh Singh Subject: [PATCH v7 27/45] x86/sev: move MSR-based VMGEXITs for CPUID to helper Date: Wed, 10 Nov 2021 16:07:13 -0600 Message-ID: <20211110220731.2396491-28-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110220731.2396491-1-brijesh.singh@amd.com> References: <20211110220731.2396491-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3ac7d9bf-ee75-4486-bab0-08d9a496a678 X-MS-TrafficTypeDiagnostic: CH2PR12MB4040: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TuM07X5hnRRgW4OrDd0pbicKavH/4fxtUvVqOzn7I3pXvtyxabzkFIqdH/MNQdPPoy1yBZw2W5sRIdBsg8UPDsQROsaDBuX//ABXIARmbvH2xyP06Mc8TLYT0V/9Um4wxQpqsSaAjc+1vw5QSLNBK5x0qHDPwo/yHQDESHA9T50LfNxhXBKsanXpSKE3ssdE9gRNoyQsFiVurM3+aNdeHzmJkWS//WBQdJ6jjr4D5iKPfM8qnIQe0YE4x8rg7lf+avY2D8ugrbkGu88tXVTClTlgQeRYDHNWU0FemhwHc1aQpOaBvOaxqgzcskz9ko8APLkCSH7oht9NtaJvxBxmjWOiLqz3QgGEyvx9isauqT9VC45zpXUx1wFmW4RPgyk0tLTTSm/5e6CWMxqBR1p0oazrOD4NxSCkmTkNiXRaoUpPceOMO4CyVrdWtW09C0v/pi2iCSuDB1k+gyC3zoQytDqWpH+WDncX7X3Z3McBPEN0sAp+W+ajjlGrunV3FuN+GOyOrRrvlvnQEmrFd2X0rqEnHl37lQ1u8CLDXm1mqTr6+uSkvKtUSzosdEDsrUoiyicaRYsxvH2DWp6Ah0JV23CGBlwdL6hcCYnoXkgsRSSIhYTZR2jOpVUr39wqoYGRZD+sowiGAtnaSTqpWyzEVrXhn9zF/v/s1hhR972HWOS9o8xV3eRvWCfyG+DcFgDnJowvW/YyVuMrIXZ2VGOUBOrY/tBgKC5U72RNy9oq7atRr6UK7jIiw2BEe2lbWIy3 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(2616005)(83380400001)(36756003)(356005)(16526019)(426003)(86362001)(82310400003)(44832011)(47076005)(70206006)(70586007)(36860700001)(7696005)(81166007)(8676002)(26005)(508600001)(7416002)(186003)(1076003)(7406005)(4326008)(5660300002)(6666004)(2906002)(54906003)(110136005)(336012)(316002)(8936002)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2021 22:08:39.3755 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ac7d9bf-ee75-4486-bab0-08d9a496a678 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4040 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: B77095000311 X-Stat-Signature: fj9non47tmfwgcgg9t5unzk73zsggg3y Authentication-Results: imf04.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=Yfjd9CYZ; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf04.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.220.50 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-HE-Tag: 1636582111-835933 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth This code will also be used later for SEV-SNP-validated CPUID code in some cases, so move it to a common helper. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/kernel/sev-shared.c | 84 +++++++++++++++++++++++++----------- 1 file changed, 58 insertions(+), 26 deletions(-) diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index b0ed64fc6520..9f81d78ab061 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -204,6 +204,58 @@ enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, bool set_ghcb_msr, return verify_exception_info(ghcb, ctxt); } +static int sev_cpuid_hv(u32 func, u32 subfunc, u32 *eax, u32 *ebx, + u32 *ecx, u32 *edx) +{ + u64 val; + + if (eax) { + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_EAX)); + VMGEXIT(); + val = sev_es_rd_ghcb_msr(); + + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + return -EIO; + + *eax = (val >> 32); + } + + if (ebx) { + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_EBX)); + VMGEXIT(); + val = sev_es_rd_ghcb_msr(); + + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + return -EIO; + + *ebx = (val >> 32); + } + + if (ecx) { + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_ECX)); + VMGEXIT(); + val = sev_es_rd_ghcb_msr(); + + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + return -EIO; + + *ecx = (val >> 32); + } + + if (edx) { + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_EDX)); + VMGEXIT(); + val = sev_es_rd_ghcb_msr(); + + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + return -EIO; + + *edx = (val >> 32); + } + + return 0; +} + /* * Boot VC Handler - This is the first VC handler during boot, there is no GHCB * page yet, so it only supports the MSR based communication with the @@ -212,39 +264,19 @@ enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, bool set_ghcb_msr, void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) { unsigned int fn = lower_bits(regs->ax, 32); - unsigned long val; + u32 eax, ebx, ecx, edx; /* Only CPUID is supported via MSR protocol */ if (exit_code != SVM_EXIT_CPUID) goto fail; - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EAX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + if (sev_cpuid_hv(fn, 0, &eax, &ebx, &ecx, &edx)) goto fail; - regs->ax = val >> 32; - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EBX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) - goto fail; - regs->bx = val >> 32; - - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_ECX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) - goto fail; - regs->cx = val >> 32; - - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EDX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) - goto fail; - regs->dx = val >> 32; + regs->ax = eax; + regs->bx = ebx; + regs->cx = ecx; + regs->dx = edx; /* * This is a VC handler and the #VC is only raised when SEV-ES is