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David Alan Gilbert" , , , , Subject: [PATCH v10 05/45] x86/boot: Introduce helpers for MSR reads/writes Date: Wed, 9 Feb 2022 12:09:59 -0600 Message-ID: <20220209181039.1262882-6-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220209181039.1262882-1-brijesh.singh@amd.com> References: <20220209181039.1262882-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e2de6007-8119-458c-84a2-08d9ebf79be1 X-MS-TrafficTypeDiagnostic: DM6PR12MB4578:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bC1x/vrbUxIpIhgHTh5NOnS6W1shK9V5Xnk13FJ1zhimmy08oESpVzj5aRDVxfrt+7xoBEs6U4uYm7JTmdYwQufNDwNK6qrWVX3ivRtayTHOxn5aXQaV/sSNfMvq1cyx+gUkYR7fhGojdDFxj6ffhzINxO3OUr3fcJQC9Ft5djfZU5eO24Jhjs7EpygqcD2tJZwx2rKQfmtoi9AyK5NyOcJ3mcGOGtitY+cP6C8wERBFL4tRbjVqdc77Hwtayq6lxai9CfbDU2NAt9100BFZOBiz4v3OIPcwwY32sxxQN/oM/IdAxve1FgXT4DZzu38O67kfEDjWjOFz/X4W1HwSM7sHLDja9qeZp1tP05ji5c+Vt37STmt+tFtLm+6RK2FLZP5pfqzSRkJghvoHgVDsHpgkBf/b/MyjpwyHtnD3JRs4qK1rMKRNsmdtveV0D5sZdyGIzsVnc1Yn9wH0HVLxnSrlcAFEuYUTtkYZjbDCUeCd0aH46APq8pxOBUfOtvLa0i8vokRB/A4IB6/fGreffcH1/TmQVeWU0iml3hsufwN3l4bHF0Z0EdkTUgEFgRitpIhTzc433v6u5E58RU0dBECXVZi9XEjSvSldJTSzfmtPslEuibFoZ1Gd73HcxGgyGyAJC7cgmNgd9YimDuZMZ3JgwnjQq0n2AE2dh9CE0SDFP6XZSjlYSBzvw+K/7vIAT0HQpqpeNHftkg+pRN6wPWDIgfTQFnDe/4VgXgpgquU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(47076005)(81166007)(316002)(356005)(54906003)(110136005)(70586007)(70206006)(36860700001)(36756003)(4326008)(8676002)(40460700003)(336012)(6666004)(2906002)(2616005)(1076003)(86362001)(26005)(7696005)(186003)(16526019)(8936002)(7406005)(5660300002)(82310400004)(83380400001)(7416002)(508600001)(44832011)(426003)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Feb 2022 18:11:35.3708 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2de6007-8119-458c-84a2-08d9ebf79be1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4578 X-Rspamd-Queue-Id: 88AF320007 Authentication-Results: imf31.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=WQNjD6EK; spf=pass (imf31.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.236.70 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com X-Stat-Signature: 4yyzu9yzcercmfk4ousfs4sjh4p8xjiw X-Rspam-User: X-Rspamd-Server: rspam10 X-HE-Tag: 1644430298-742766 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth The current set of helpers used throughout the run-time kernel have dependencies on code/facilities outside of the boot kernel, so there are a number of call-sites throughout the boot kernel where inline assembly is used instead. More will be added with subsequent patches that add support for SEV-SNP, so take the opportunity to provide a basic set of helpers that can be used by the boot kernel to reduce reliance on inline assembly. Use boot_* prefix so that it's clear these are helpers specific to the boot kernel to avoid any confusion with the various other MSR read/write helpers. Suggested-by: Borislav Petkov Signed-off-by: Michael Roth --- arch/x86/boot/msr.h | 28 ++++++++++++++++++++++++++++ arch/x86/include/asm/msr.h | 11 +---------- arch/x86/include/asm/shared/msr.h | 15 +++++++++++++++ 3 files changed, 44 insertions(+), 10 deletions(-) create mode 100644 arch/x86/boot/msr.h create mode 100644 arch/x86/include/asm/shared/msr.h diff --git a/arch/x86/boot/msr.h b/arch/x86/boot/msr.h new file mode 100644 index 000000000000..b6bb2161da27 --- /dev/null +++ b/arch/x86/boot/msr.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Helpers/definitions related to MSR access. + */ + +#ifndef BOOT_MSR_H +#define BOOT_MSR_H + +#include + +/* + * The kernel proper already defines rdmsr()/wrmsr(), but they are not for the + * boot kernel since they rely tracepoint/exception handling infrastructure + * that's not available here, hence these boot_{rd,wr}msr helpers which serve + * the singular purpose of wrapping the RDMSR/WRMSR instructions to reduce the + * need for inline assembly calls throughout the boot kernel code. + */ +static inline void boot_rdmsr(unsigned int msr, struct msr *m) +{ + asm volatile("rdmsr" : "=a" (m->l), "=d" (m->h) : "c" (msr)); +} + +static inline void boot_wrmsr(unsigned int msr, const struct msr *m) +{ + asm volatile("wrmsr" : : "c" (msr), "a"(m->l), "d" (m->h) : "memory"); +} + +#endif /* BOOT_MSR_H */ diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index d42e6c6b47b1..65ec1965cd28 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -10,16 +10,7 @@ #include #include #include - -struct msr { - union { - struct { - u32 l; - u32 h; - }; - u64 q; - }; -}; +#include struct msr_info { u32 msr_no; diff --git a/arch/x86/include/asm/shared/msr.h b/arch/x86/include/asm/shared/msr.h new file mode 100644 index 000000000000..1e6ec10b3a15 --- /dev/null +++ b/arch/x86/include/asm/shared/msr.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_SHARED_MSR_H +#define _ASM_X86_SHARED_MSR_H + +struct msr { + union { + struct { + u32 l; + u32 h; + }; + u64 q; + }; +}; + +#endif /* _ASM_X86_SHARED_MSR_H */