From patchwork Sun Mar 20 00:07:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nadav Amit X-Patchwork-Id: 12786387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC9A3C433F5 for ; Sun, 20 Mar 2022 00:06:46 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 73A528D0003; Sat, 19 Mar 2022 20:06:46 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 6E9C98D0001; Sat, 19 Mar 2022 20:06:46 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 5B24E8D0003; Sat, 19 Mar 2022 20:06:46 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0150.hostedemail.com [216.40.44.150]) by kanga.kvack.org (Postfix) with ESMTP id 49DC08D0001 for ; Sat, 19 Mar 2022 20:06:46 -0400 (EDT) Received: from smtpin26.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay05.hostedemail.com (Postfix) with ESMTP id E797C181CB2CA for ; Sun, 20 Mar 2022 00:06:45 +0000 (UTC) X-FDA: 79262823612.26.489CFEB Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) by imf24.hostedemail.com (Postfix) with ESMTP id 62A5A180032 for ; Sun, 20 Mar 2022 00:06:45 +0000 (UTC) Received: by mail-pl1-f177.google.com with SMTP id p17so9858259plo.9 for ; Sat, 19 Mar 2022 17:06:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EneRWVgWQxrY1C12VG15OjPWHgql2L2aCtdoR7Sm4pM=; b=JXLg5HFtAOkvtS8q/ZDF+fC7rtvvrWLHqtnkq1waxlLm1ENKt2S+B4ie82Nr0wkgwi pRgPsC0AfIbuXVsUb+Vt8aGqY9DUblUHDkCHoi/B1hw0aGa9TFVJIeKM1hNhwKmeNrcp mNkiuH5NMgRmjJNt/uXmXVmVrNxHsitQWej6GbAraje/jBSw1Q64TgY+pncz6Mcl6L86 xQ0wKD7ibORWvz9CKDimJ9FFfFOOCvgsD7JAFgQJ+8RCQ0Z2L8OhQnPkTmk+19q4Jrd6 b2Z0IRqZ2DJkPuxLd1CvlTjF8LUXdMirp9+0JMjfrf3WwN3PZ36JRZ2Vxa/OtzAgTC1E HIqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EneRWVgWQxrY1C12VG15OjPWHgql2L2aCtdoR7Sm4pM=; b=5PEQeq7MP9nvyVyf6OVRc/kF6LUhJ4VgJt/bV0g1omV9yU+HQxxHWTGsH56o5LMSch r2gPZga0U85Ah3Rb17iNzE6IwUScOcrRxKAC7fqDOD/O5WkscK2g7TzYKnLwrdV/J9vZ 9M6HfSwa9AOeGPFOyDcz3gJGo5MdOxOh2djLi00ftnnnL0GI42/vDZ0pU4wm2WYWDRDP ptbzwKcaU/e8jLJUxBAUH1Ko9Agiq0UeKkUOnUsCzPghxShrxhq9eJ011ZPNiWrx+DSX 1Vt+/PizUQbXzSn7zprYtXLuGOR08XEfWyH5V4QBbhSyI5gyXz1MJ/3EdltCyZPL/SFs +nfg== X-Gm-Message-State: AOAM531BlhQCqsFErj69F7wshT1IiFziuNDOW5ahfQoByJkY/FScBw17 HQ9d0aruUPan1F4ixcx+oWk= X-Google-Smtp-Source: ABdhPJwoLzmTUpgkB2qeni2yJYYchDAW317jN/xzudnFZ56RyH9Z/9K/UODDGBA31tCa1ZgoPUjoLA== X-Received: by 2002:a17:90a:4a06:b0:1c6:d786:10a8 with SMTP id e6-20020a17090a4a0600b001c6d78610a8mr5035281pjh.207.1647734804292; Sat, 19 Mar 2022 17:06:44 -0700 (PDT) Received: from sc2-haas01-esx0118.eng.vmware.com ([66.170.99.1]) by smtp.gmail.com with ESMTPSA id ep2-20020a17090ae64200b001c6a7c22aedsm5550124pjb.37.2022.03.19.17.06.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Mar 2022 17:06:43 -0700 (PDT) From: Nadav Amit X-Google-Original-From: Nadav Amit To: Andrew Morton Cc: linux-mm@kvack.org, Nadav Amit , Andrea Arcangeli , Andrew Cooper , Andy Lutomirski , Dave Hansen , Peter Xu , Peter Zijlstra , Thomas Gleixner , Will Deacon , Yu Zhao , Nick Piggin , x86@kernel.org Subject: [RESEND PATCH v5 3/3] mm: avoid unnecessary flush on change_huge_pmd() Date: Sat, 19 Mar 2022 17:07:19 -0700 Message-Id: <20220320000719.1533862-4-namit@vmware.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220320000719.1533862-1-namit@vmware.com> References: <20220320000719.1533862-1-namit@vmware.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: 62A5A180032 X-Stat-Signature: ucbwqkkxbaycxdk1po37a1y3rroy11xz Authentication-Results: imf24.hostedemail.com; dkim=pass header.d=gmail.com header.s=20210112 header.b=JXLg5HFt; spf=none (imf24.hostedemail.com: domain of mail-pl1-f177.google.com has no SPF policy when checking 209.85.214.177) smtp.helo=mail-pl1-f177.google.com; dmarc=pass (policy=none) header.from=gmail.com X-HE-Tag: 1647734805-627383 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Nadav Amit Calls to change_protection_range() on THP can trigger, at least on x86, two TLB flushes for one page: one immediately, when pmdp_invalidate() is called by change_huge_pmd(), and then another one later (that can be batched) when change_protection_range() finishes. The first TLB flush is only necessary to prevent the dirty bit (and with a lesser importance the access bit) from changing while the PTE is modified. However, this is not necessary as the x86 CPUs set the dirty-bit atomically with an additional check that the PTE is (still) present. One caveat is Intel's Knights Landing that has a bug and does not do so. Leverage this behavior to eliminate the unnecessary TLB flush in change_huge_pmd(). Introduce a new arch specific pmdp_invalidate_ad() that only invalidates the access and dirty bit from further changes. Cc: Andrea Arcangeli Cc: Andrew Cooper Cc: Andrew Morton Cc: Andy Lutomirski Cc: Dave Hansen Cc: Peter Xu Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Will Deacon Cc: Yu Zhao Cc: Nick Piggin Cc: x86@kernel.org Signed-off-by: Nadav Amit --- arch/x86/include/asm/pgtable.h | 5 +++++ arch/x86/mm/pgtable.c | 10 ++++++++++ include/linux/pgtable.h | 20 ++++++++++++++++++++ mm/huge_memory.c | 4 ++-- mm/pgtable-generic.c | 8 ++++++++ 5 files changed, 45 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index 62ab07e24aef..23ad34edcc4b 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -1173,6 +1173,11 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, } } #endif + +#define __HAVE_ARCH_PMDP_INVALIDATE_AD +extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, + unsigned long address, pmd_t *pmdp); + /* * Page table pages are page-aligned. The lower half of the top * level is used for userspace and the top half for the kernel. diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index 3481b35cb4ec..f16059e9a85e 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -608,6 +608,16 @@ int pmdp_clear_flush_young(struct vm_area_struct *vma, return young; } + +pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, unsigned long address, + pmd_t *pmdp) +{ + /* + * No flush is necessary. Once an invalid PTE is established, the PTE's + * access and dirty bits cannot be updated. + */ + return pmdp_establish(vma, address, pmdp, pmd_mkinvalid(*pmdp)); +} #endif /** diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h index f4f4077b97aa..5826e8e52619 100644 --- a/include/linux/pgtable.h +++ b/include/linux/pgtable.h @@ -570,6 +570,26 @@ extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, pmd_t *pmdp); #endif +#ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD + +/* + * pmdp_invalidate_ad() invalidates the PMD while changing a transparent + * hugepage mapping in the page tables. This function is similar to + * pmdp_invalidate(), but should only be used if the access and dirty bits would + * not be cleared by the software in the new PMD value. The function ensures + * that hardware changes of the access and dirty bits updates would not be lost. + * + * Doing so can allow in certain architectures to avoid a TLB flush in most + * cases. Yet, another TLB flush might be necessary later if the PMD update + * itself requires such flush (e.g., if protection was set to be stricter). Yet, + * even when a TLB flush is needed because of the update, the caller may be able + * to batch these TLB flushing operations, so fewer TLB flush operations are + * needed. + */ +extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, + unsigned long address, pmd_t *pmdp); +#endif + #ifndef __HAVE_ARCH_PTE_SAME static inline int pte_same(pte_t pte_a, pte_t pte_b) { diff --git a/mm/huge_memory.c b/mm/huge_memory.c index 51b0f3cb1ba0..691d80edcfd7 100644 --- a/mm/huge_memory.c +++ b/mm/huge_memory.c @@ -1781,10 +1781,10 @@ int change_huge_pmd(struct mmu_gather *tlb, struct vm_area_struct *vma, * The race makes MADV_DONTNEED miss the huge pmd and don't clear it * which may break userspace. * - * pmdp_invalidate() is required to make sure we don't miss + * pmdp_invalidate_ad() is required to make sure we don't miss * dirty/young flags set by hardware. */ - oldpmd = pmdp_invalidate(vma, addr, pmd); + oldpmd = pmdp_invalidate_ad(vma, addr, pmd); entry = pmd_modify(oldpmd, newprot); if (preserve_write) diff --git a/mm/pgtable-generic.c b/mm/pgtable-generic.c index 6523fda274e5..90ab721a12a8 100644 --- a/mm/pgtable-generic.c +++ b/mm/pgtable-generic.c @@ -201,6 +201,14 @@ pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, } #endif +#ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD +pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, unsigned long address, + pmd_t *pmdp) +{ + return pmdp_invalidate(vma, address, pmdp); +} +#endif + #ifndef pmdp_collapse_flush pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address, pmd_t *pmdp)