diff mbox series

[1/2] riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte

Message ID 20221023133205.3493564-2-guoren@kernel.org (mailing list archive)
State New
Headers show
Series Enable ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP & fixup race condition on PG_dcache_clean | expand

Commit Message

Guo Ren Oct. 23, 2022, 1:32 p.m. UTC 
From: Guo Ren <guoren@linux.alibaba.com>

RISC-V follows the arm64 flush_icache_pte mechanism and also includes
its bug. The patch ensures that instructions are observable in a new
mapping. For more details, see 588a513d3425 ("arm64: Fix race condition
on PG_dcache_clean in __sync_icache_dcache()").

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Steven Price <steven.price@arm.com>
---
 arch/riscv/mm/cacheflush.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 6cb7d96ad9c7..7c9f97fa3938 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -82,7 +82,9 @@  void flush_icache_pte(pte_t pte)
 {
 	struct page *page = pte_page(pte);
 
-	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+	if (!test_bit(PG_dcache_clean, &page->flags)) {
 		flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
+	}
 }
 #endif /* CONFIG_MMU */