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dkim=pass header.d=kernel.org header.s=k20201202 header.b=J+LaVmkY; spf=pass (imf20.hostedemail.com: domain of guoren@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=guoren@kernel.org; dmarc=pass (policy=none) header.from=kernel.org X-Rspam-User: X-Rspamd-Server: rspam01 X-HE-Tag: 1666532035-626574 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Guo Ren RISC-V follows the arm64 flush_icache_pte mechanism and also includes its bug. The patch ensures that instructions are observable in a new mapping. For more details, see 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean in __sync_icache_dcache()"). Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Catalin Marinas Cc: Will Deacon Cc: Steven Price --- arch/riscv/mm/cacheflush.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6cb7d96ad9c7..7c9f97fa3938 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -82,7 +82,9 @@ void flush_icache_pte(pte_t pte) { struct page *page = pte_page(pte); - if (!test_and_set_bit(PG_dcache_clean, &page->flags)) + if (!test_bit(PG_dcache_clean, &page->flags)) { flush_icache_all(); + set_bit(PG_dcache_clean, &page->flags); + } } #endif /* CONFIG_MMU */