@@ -22,6 +22,7 @@ config ARM64
select ARCH_HAS_CURRENT_STACK_POINTER
select ARCH_HAS_DEBUG_VIRTUAL
select ARCH_HAS_DEBUG_VM_PGTABLE
+ select ARCH_HAS_DMA_CACHE_LINE_SIZE
select ARCH_HAS_DMA_PREP_COHERENT
select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
select ARCH_HAS_FAST_MULTIPLIER
@@ -545,6 +545,8 @@ static inline int dma_set_min_align_mask(struct device *dev,
static inline int dma_get_cache_alignment(void)
{
+ if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CACHE_LINE_SIZE))
+ return cache_line_size();
#ifdef ARCH_HAS_DMA_MINALIGN
return ARCH_DMA_MINALIGN;
#endif
@@ -76,6 +76,12 @@ config ARCH_HAS_DMA_PREP_COHERENT
config ARCH_HAS_FORCE_DMA_UNENCRYPTED
bool
+config ARCH_HAS_DMA_CACHE_LINE_SIZE
+ bool
+ help
+ Select if the architecture has non-coherent DMA and
+ cache_line_size() is a safe alignment for DMA buffers.
+
config SWIOTLB
bool
select NEED_DMA_MAP_STATE
On architectures like arm64, ARCH_DMA_MINALIGN is larger than the majority of cache line size configurations. Allow an architecture to opt in to dma_get_cache_alignment() returning such smaller size and select the option for arm64. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Will Deacon <will@kernel.org> --- Is there any architecture where ARCH_DMA_MINALIGN is larger than cache_line_size()? We could avoid another Kconfig entry. arch/arm64/Kconfig | 1 + include/linux/dma-mapping.h | 2 ++ kernel/dma/Kconfig | 6 ++++++ 3 files changed, 9 insertions(+)