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Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , Linus Torvalds , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv13 02/16] x86: CPUID and CR3/CR4 flags for Linear Address Masking Date: Tue, 27 Dec 2022 06:08:15 +0300 Message-Id: <20221227030829.12508-3-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.2 In-Reply-To: <20221227030829.12508-1-kirill.shutemov@linux.intel.com> References: <20221227030829.12508-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Queue-Id: 3D12A1A0004 X-Rspamd-Server: rspam01 X-Stat-Signature: nqwmxa36b3ughb6cx3hys4cr457wj3x7 X-HE-Tag: 1672110524-376515 X-HE-Meta: U2FsdGVkX1+icBrrOw1bbepVbeFZVRueP4yU/PbYWljo/F3F/H5e8uKl7ycqfpidF0uoZ07xUCZW0R4bU+BP/2zJND0toWad04O2bgLnyerYDNX36OwGy4gutgs3hr9uqT6di/cAK4zTW8yBN2I/K0YmnbDQXy6h5osyA4D8lj5NylVc20Tr5Xt20Ou7aj+Kka77ZP84PRi2FBQtwxy+0GqZAx7Yhk/Cj2qkkRTfUENyIIzNBcsdcFgrAvl9v0Ef5zFuTsW1/9deATcfadDx4dZjYO3FEj9tNJqmYNfjEirOAwEhEISYFGOEvm8inBntK71CWNQLdpZCVpkORcfWttjHqk4ixN56f3AQWAQ3DSOCUD9NM1aUha0REKfDfKjQOPSHL6FwJpY111JC9kAC+B0CePCNWSOkwKh2gjAR389Gjp6TeWuq1ukOI1SZcSbvkc8EESLTefIwtHmTdqPBlPcRAC4rRoHr2jieCvgvb2IKG4eRA/PjQpPZmQt0BAs4y1bf5bdjJY3lrtr8UuiFcwHKrUr7AOHLDxd5Iz9FFGNuXxD/CZgfbsSmMku0+DY6av0/a2PbefcGG2BDMP1roDOS9qDSGYyJOSvV74UlgOBEZOgHZ2ILQqdvvHYmFW2mRHvltz2VJgt0W6ZqUvFcvlQQ5J0mOdk6PjqzmjmlAXefFRh85vZ+decVxozh1b5RTPFA/XeNDW01BCW7Qc69PQPoQo0kY00lx//fV0fDvzflxDCizYAByoNhJfe6w1Ebmyj5qIPzj4BWcKBBBD8Mo6gB0bhjzVX61Hbf440QbngLu92sbCWxrjpLo23/ISoHly3t3Fb0oveYlQ66n50+DNkYeZR5LvgS4exVZ8rCYWKRfbGJwm0tpvgEJNYn4njKUSDA3RK7U87asP7KqMXrVlHtb7a0k2PDwRmhWRadYqS504L1cj8cVDWRl9oMdzpM6bZOqciS53s= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Enumerate Linear Address Masking and provide defines for CR3 and CR4 flags. Signed-off-by: Kirill A. Shutemov Reviewed-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) Tested-by: Alexander Potapenko --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/processor-flags.h | 2 ++ arch/x86/include/uapi/asm/processor-flags.h | 6 ++++++ 3 files changed, 9 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 61012476d66e..bc662c80b99d 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -314,6 +314,7 @@ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ +#define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index a7f3d9100adb..d8cccadc83a6 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -28,6 +28,8 @@ * On systems with SME, one bit (in a variable position!) is stolen to indicate * that the top-level paging structure is encrypted. * + * On systemms with LAM, bits 61 and 62 are used to indicate LAM mode. + * * All of the remaining bits indicate the physical address of the top-level * paging structure. * diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index c47cc7f2feeb..d898432947ff 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -82,6 +82,10 @@ #define X86_CR3_PCID_BITS 12 #define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL)) +#define X86_CR3_LAM_U57_BIT 61 /* Activate LAM for userspace, 62:57 bits masked */ +#define X86_CR3_LAM_U57 _BITULL(X86_CR3_LAM_U57_BIT) +#define X86_CR3_LAM_U48_BIT 62 /* Activate LAM for userspace, 62:48 bits masked */ +#define X86_CR3_LAM_U48 _BITULL(X86_CR3_LAM_U48_BIT) #define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */ #define X86_CR3_PCID_NOFLUSH _BITULL(X86_CR3_PCID_NOFLUSH_BIT) @@ -132,6 +136,8 @@ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) #define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology */ #define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) +#define X86_CR4_LAM_SUP_BIT 28 /* LAM for supervisor pointers */ +#define X86_CR4_LAM_SUP _BITUL(X86_CR4_LAM_SUP_BIT) /* * x86-64 Task Priority Register, CR8