From patchwork Thu Jan 19 21:23:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgecombe, Rick P" X-Patchwork-Id: 13108814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D9B0C46467 for ; Thu, 19 Jan 2023 21:24:33 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 63AA528000D; Thu, 19 Jan 2023 16:24:25 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 5C280280001; Thu, 19 Jan 2023 16:24:25 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 3AC2228000D; Thu, 19 Jan 2023 16:24:25 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id 25683280001 for ; Thu, 19 Jan 2023 16:24:25 -0500 (EST) Received: from smtpin13.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id F172D1C6571 for ; Thu, 19 Jan 2023 21:24:24 +0000 (UTC) X-FDA: 80372827248.13.81C5051 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by imf16.hostedemail.com (Postfix) with ESMTP id F0FD3180002 for ; Thu, 19 Jan 2023 21:24:22 +0000 (UTC) Authentication-Results: imf16.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=nG6ZywQW; spf=pass (imf16.hostedemail.com: domain of rick.p.edgecombe@intel.com designates 192.55.52.93 as permitted sender) smtp.mailfrom=rick.p.edgecombe@intel.com; dmarc=pass (policy=none) header.from=intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1674163463; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references:dkim-signature; bh=UIaubgF5cxlgy9UntqyzMGFahvGgA9BhdHUjWEg2kcA=; b=JM7Xd7hpIfLNh2QA4YoRD69DcZujHian9ooinQG+bu1SiFm0T+yJK9PBLHKhOspjTkbg4G 5jH3dc3CbFx34QzOoocX7yoWfZbjOo6f6VGEIHc9Qi5BTmHjBvhtmgjpTackuZldGz08+4 NKYT2Awt1vQrYFL9nb7F4OBUpadnWCU= ARC-Authentication-Results: i=1; imf16.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=nG6ZywQW; spf=pass (imf16.hostedemail.com: domain of rick.p.edgecombe@intel.com designates 192.55.52.93 as permitted sender) smtp.mailfrom=rick.p.edgecombe@intel.com; dmarc=pass (policy=none) header.from=intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1674163463; a=rsa-sha256; cv=none; b=BA7F3DudyG9Zyc+CKLezVhj3Sq86aoWeQXJqThKtiSm9KXa/kr4L4JN0zZ4YRhe0wfMCRt lRkRQjQzFyK0BYP/84ZLY7xEG0x79w1bBRpY8YFSeMAburNGSf5xD25tDd1OXZXjHbt7YL KIVC4fXelaoDFfZRwxN6f0QgRZGL/6I= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674163463; x=1705699463; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Y8HP+6SI6A4E79h0YyqSt+wn/k0j51I/AMnEXqlWOFs=; b=nG6ZywQW3X45sxUg6+EVOduvXjjCPAU3k6fs1Hr/xHTqEUvwbVVRAyTw g0E8qOySNoqUDUphLnD11AuAg4lBvOx2KJjjAFQ89iJg4L3jxdEyNHyoa kG6A7cUBG9SRWc0pvfcdYWn6s6pqUL0bSranA/TcqByZr4V7kTmcKwt45 JmZscj5lG6Q7RHhM/gONCK5LUhKaCqqOuKkcWGrTm5HRf5Nvu3dAkEt/a hkUtbYas/blQUDuxG+bSxzyPIHnXYVPMG+AMHdlieX0uUvODOtMvqJE4f uOO/Uyt0NGQOv+2mp3y04cVjnB5vDWJN1c+gJF9tIBADcaZYD2dsPmgVc Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10595"; a="323120044" X-IronPort-AV: E=Sophos;i="5.97,230,1669104000"; d="scan'208";a="323120044" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2023 13:24:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10595"; a="989139185" X-IronPort-AV: E=Sophos;i="5.97,230,1669104000"; d="scan'208";a="989139185" Received: from hossain3-mobl.amr.corp.intel.com (HELO rpedgeco-desk.amr.corp.intel.com) ([10.252.128.187]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2023 13:24:20 -0800 From: Rick Edgecombe To: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , Weijiang Yang , "Kirill A . Shutemov" , John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, akpm@linux-foundation.org, Andrew.Cooper3@citrix.com, christina.schimpe@intel.com Cc: rick.p.edgecombe@intel.com Subject: [PATCH v5 36/39] x86/fpu: Add helper for initing features Date: Thu, 19 Jan 2023 13:23:14 -0800 Message-Id: <20230119212317.8324-37-rick.p.edgecombe@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119212317.8324-1-rick.p.edgecombe@intel.com> References: <20230119212317.8324-1-rick.p.edgecombe@intel.com> X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: F0FD3180002 X-Stat-Signature: pjmkxsq4kjp5whyhske3phj4kco8yn6n X-Rspam-User: X-HE-Tag: 1674163462-190073 X-HE-Meta: U2FsdGVkX1/aM2t4inLICzkaBInsdMKGrmta6I6mjM8NiBj9VI00SlQV/bZSME3F7307MMXTFOS2fhAzGAhPSwQou/yHnTlInJjIdGEQtKk+qPg5SQluEeL6DBqOG5iOjqIVMIMql+t9t6m4gn4PiMlaFk3Wn16G/ObOK6r8iNhV4OiOovj0tmc7mYelkqDmVeQ4WKsHR7yjCXmTn0X2d1vYFxr3XKOejYb51+oLEmhvEU59IIDJXQ1WqQk4TBtp66pdMyqsZLoWlfGeqaLjuaE+VgTqdS9H8LTiGdqSo/SDDNYGOXCebyKEU/Buv6HnwdFDRTh1nePdOWfbjnNcXrOcSaBW/nykFXYrQrkgjBSBDYqdFL9f977N6q9sFQ/cEtcfDThIoFWSjE3MGSpAS/AzH9F1dY8giZcAlqeejPPDNOkQ/af11XaWHYsowmWHyxP40Vr8k4Y9RzMgGR7EQ/oNPwTU0dccnYUFO/YSO9jyL1BzuKdNpTN43d648GIN2SvumolaA9d+mnGJvb7COP9cnn4vLxejHEaruxnKkog0y08htDOiounZOiABv7voZywshbTHsdX8l/hO1NUabw+lzcAwvjWTrOEDVh2JRDxf7L32+tncV86mVJrsBFqIfIlUoiL0KX9W8p0cRnlHpm8Pz+0zYY8WzIY1cIXNSV7/n1Pw/HaiqNMmUNrK/lBNPfwW2aNGChUqTisZ4lpvMMtgBMPNwoRD0FUsneoNovuUqH6gQ0JtnqQRiq3LgmCNNmR3vhukhkUt9CvkK+d3vCXWU4te/fd6S71oLfMoUUxK+EFEvJIynyKO91GFvfVzpLIfk19U9daAnb4nhIvRK/QIYdR308FDMFbyJoH7m/AI6XX0sugF0wff23umpt0gP6fBaP4X1ze7DcBvqJmExastYOsiFb+VfyTDfeX2nkAhpxYXUItdxSqiRohWrNANFbdT8YsitHFuRDWLwxL CP19yTom RewQO6djpKV9R2m7RXn/gLbjDs0lGCWNOQgd790b8bTT4CWJtcIEQ7VCSGN1IUy5d6Ii2FOhsqLJt1XWSbMXJ8SVO0+R1GpOx/i4MsDExWuc/Bhg1GMJ7NVEhQm78UWC22hEFuGhh5rRa2AH4ugWvlnP0hUxOZCWjDm23Z7BMpSVq9oeT+R+7F5H1RYhPWx0Px+1PvY2yQcXiFAVVZP9u+CH8igAm4v8NzBS8+CLqX6JdTaY= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: If an xfeature is saved in a buffer, the xfeature's bit will be set in xsave->header.xfeatures. The CPU may opt to not save the xfeature if it is in it's init state. In this case the xfeature buffer address cannot be retrieved with get_xsave_addr(). Future patches will need to handle the case of writing to an xfeature that may not be saved. So provide helpers to init an xfeature in an xsave buffer. This could of course be done directly by reaching into the xsave buffer, however this would not be robust against future changes to optimize the xsave buffer by compacting it. In that case the xsave buffer would need to be re-arranged as well. So the logic properly belongs encapsulated in a helper where the logic can be unified. Tested-by: Pengfei Xu Tested-by: John Allen Signed-off-by: Rick Edgecombe --- v2: - New patch arch/x86/kernel/fpu/xstate.c | 58 +++++++++++++++++++++++++++++------- arch/x86/kernel/fpu/xstate.h | 6 ++++ 2 files changed, 53 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 13a80521dd51..3ff80be0a441 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -934,6 +934,24 @@ static void *__raw_xsave_addr(struct xregs_state *xsave, int xfeature_nr) return (void *)xsave + xfeature_get_offset(xcomp_bv, xfeature_nr); } +static int xsave_buffer_access_checks(int xfeature_nr) +{ + /* + * Do we even *have* xsave state? + */ + if (!boot_cpu_has(X86_FEATURE_XSAVE)) + return 1; + + /* + * We should not ever be requesting features that we + * have not enabled. + */ + if (WARN_ON_ONCE(!xfeature_enabled(xfeature_nr))) + return 1; + + return 0; +} + /* * Given the xsave area and a state inside, this function returns the * address of the state. @@ -954,17 +972,7 @@ static void *__raw_xsave_addr(struct xregs_state *xsave, int xfeature_nr) */ void *get_xsave_addr(struct xregs_state *xsave, int xfeature_nr) { - /* - * Do we even *have* xsave state? - */ - if (!boot_cpu_has(X86_FEATURE_XSAVE)) - return NULL; - - /* - * We should not ever be requesting features that we - * have not enabled. - */ - if (WARN_ON_ONCE(!xfeature_enabled(xfeature_nr))) + if (xsave_buffer_access_checks(xfeature_nr)) return NULL; /* @@ -984,6 +992,34 @@ void *get_xsave_addr(struct xregs_state *xsave, int xfeature_nr) return __raw_xsave_addr(xsave, xfeature_nr); } +/* + * Given the xsave area and a state inside, this function + * initializes an xfeature in the buffer. + * + * get_xsave_addr() will return NULL if the feature bit is + * not present in the header. This function will make it so + * the xfeature buffer address is ready to be retrieved by + * get_xsave_addr(). + * + * Inputs: + * xstate: the thread's storage area for all FPU data + * xfeature_nr: state which is defined in xsave.h (e.g. XFEATURE_FP, + * XFEATURE_SSE, etc...) + * Output: + * 1 if the feature cannot be inited, 0 on success + */ +int init_xfeature(struct xregs_state *xsave, int xfeature_nr) +{ + if (xsave_buffer_access_checks(xfeature_nr)) + return 1; + + /* + * Mark the feature inited. + */ + xsave->header.xfeatures |= BIT_ULL(xfeature_nr); + return 0; +} + #ifdef CONFIG_ARCH_HAS_PKEYS /* diff --git a/arch/x86/kernel/fpu/xstate.h b/arch/x86/kernel/fpu/xstate.h index a4ecb04d8d64..dc06f63063ee 100644 --- a/arch/x86/kernel/fpu/xstate.h +++ b/arch/x86/kernel/fpu/xstate.h @@ -54,6 +54,12 @@ extern void fpu__init_cpu_xstate(void); extern void fpu__init_system_xstate(unsigned int legacy_size); extern void *get_xsave_addr(struct xregs_state *xsave, int xfeature_nr); +extern int init_xfeature(struct xregs_state *xsave, int xfeature_nr); + +static inline int xfeature_saved(struct xregs_state *xsave, int xfeature_nr) +{ + return xsave->header.xfeatures & BIT_ULL(xfeature_nr); +} static inline u64 xfeatures_mask_supervisor(void) {