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Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , Linus Torvalds , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv15 03/17] x86: CPUID and CR3/CR4 flags for Linear Address Masking Date: Tue, 24 Jan 2023 01:04:46 +0300 Message-Id: <20230123220500.21077-4-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230123220500.21077-1-kirill.shutemov@linux.intel.com> References: <20230123220500.21077-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 74CD512000C X-Stat-Signature: pn154eaxszokeucipqibns5hmx436u86 X-Rspam-User: X-HE-Tag: 1674511531-243676 X-HE-Meta: U2FsdGVkX1/v3W0QExgFUQE42dC2g91CAFuJIRD+abAlzaK0JXBHSxQF4SnE1KrYXeTjGydsjGdhpHikCQS3MeYnVz3CR/z3/HyBSRn7BU+Ss68Gl6+npmMpiQDwgOv3VSLPqJe/JV+yOp8REAyfKznC3X80DgTEtb4S+W1HULt2A4eHgqPr1snlQf7LqiuhCoaxZgtvLiZfbRir77pMDmEsYGBZenqTCknWZDdU0Qv1nPjWGcGxId0dqL/64x2uYK1U6vAf13pX3ewNDh5mKjZUDFUjTsfB2uX/baQyhEavkcUzLQJkH4f4KR6F+cbwf5Ywt6eXosuXew6fHP38uEIftuEJbdYTAKht0y1gK/2RKP4EqvGnuhNYACEOhNoUEY4ur/J7Pb6Mo9QffOsgHh7u84B7Z8xm8Rusw0zWmsARWjwpOk5vIXkQb2uBCEsZjUfWO/OJ7x0Q0R7IFK9CQiGeMUV+GxxQQFct64+8LJAbxk9yJADs/OMEucGxkK+9ctA2ydMt7oT5XuGdjTPo4plhgDriHiFZIVvvzVzEz1yRswGHyKzR5ezLstzNCApO58tEKpxKoZ6FXbncc8738wH6DdfvPqOhHiEISxEriL28nU0kvizIfP3YqRNqvUZMOWHp0icVL5nwgbncpejVi1zKpp7ACQ13O2zMWGqXGQKP9bwBY0p/QbFrTtT2QYE3DAhvZzpwjW1qns0h883H4tj9M48MN2pdsNKNcXjVwG9eZ1VgJjM2hPDNWHfdB0JpXS/bH8Q8bwQVFzNPa00s/g/FMbWooFp3/0p9eivp1szA3tLmYsgiwoj9+XT3McU/GsZAtzWCoG4/V4qZLGX2es9rKUda9a2NYwsOIzYCrCIq/NeIqhT0cbSlfhE8dS+zeEVT58iZEp3iUeZ+mB72XB7ontBWq2X1zRKk0TqLul+4G6bAlBncp8PVIRR56ktSvmhCetbt/gy6pfXGDvA 4LnFCawS oDO4y7YU/YmNqISV/jjnV67dzKHbzQcLycvkcbcX1CA8VymSa6tVHG8WBv0+BQqJPv161hxV0QWfUdbAPxWgybpXnJ5dDQ1Np25RChHp2jjeDJYgMlhGwOVoOhdum0VkJ9MvdSTl9j9oS4//0qZzzjSWTtRi+kLUl3M1BDG5qrZykPMoQRxIGFfQQ+e67m4WWfj0HyCUHlSPH0ZHmaNEntrwsSpTHfabENszBK3UeSHsy87Y7LP+1/mSGQR1/8Ln8I0tSZS1dB0QZCcExeV6sBXAmzTp6YbUaQBt8BC8/S+C+FCDWCNU6rx6Wpup0GKJYWVABDTcH21wVbDx/Th1qJavqS1K1YpddnMl6snP/mploaxo= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Enumerate Linear Address Masking and provide defines for CR3 and CR4 flags. The new CONFIG_ADDRESS_MASKING option enables the feature support in kernel. Signed-off-by: Kirill A. Shutemov Reviewed-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) Tested-by: Alexander Potapenko --- arch/x86/Kconfig | 11 +++++++++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/processor-flags.h | 2 ++ arch/x86/include/uapi/asm/processor-flags.h | 6 ++++++ 4 files changed, 20 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3604074a878b..211869aa618d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2290,6 +2290,17 @@ config RANDOMIZE_MEMORY_PHYSICAL_PADDING If unsure, leave at the default value. +config ADDRESS_MASKING + bool "Linear Address Masking support" + depends on X86_64 + help + Linear Address Masking (LAM) modifies the checking that is applied + to 64-bit linear addresses, allowing software to use of the + untranslated address bits for metadata. + + The capability can be used for efficient address sanitizers (ASAN) + implementation and for optimizations in JITs. + config HOTPLUG_CPU def_bool y depends on SMP diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 61012476d66e..bc662c80b99d 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -314,6 +314,7 @@ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ +#define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index a7f3d9100adb..d8cccadc83a6 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -28,6 +28,8 @@ * On systems with SME, one bit (in a variable position!) is stolen to indicate * that the top-level paging structure is encrypted. * + * On systemms with LAM, bits 61 and 62 are used to indicate LAM mode. + * * All of the remaining bits indicate the physical address of the top-level * paging structure. * diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index c47cc7f2feeb..d898432947ff 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -82,6 +82,10 @@ #define X86_CR3_PCID_BITS 12 #define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL)) +#define X86_CR3_LAM_U57_BIT 61 /* Activate LAM for userspace, 62:57 bits masked */ +#define X86_CR3_LAM_U57 _BITULL(X86_CR3_LAM_U57_BIT) +#define X86_CR3_LAM_U48_BIT 62 /* Activate LAM for userspace, 62:48 bits masked */ +#define X86_CR3_LAM_U48 _BITULL(X86_CR3_LAM_U48_BIT) #define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */ #define X86_CR3_PCID_NOFLUSH _BITULL(X86_CR3_PCID_NOFLUSH_BIT) @@ -132,6 +136,8 @@ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) #define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology */ #define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) +#define X86_CR4_LAM_SUP_BIT 28 /* LAM for supervisor pointers */ +#define X86_CR4_LAM_SUP _BITUL(X86_CR4_LAM_SUP_BIT) /* * x86-64 Task Priority Register, CR8