From patchwork Sat Feb 18 21:14:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Edgecombe X-Patchwork-Id: 13145678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27F88C6379F for ; Sat, 18 Feb 2023 21:17:07 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id BFFF5280026; Sat, 18 Feb 2023 16:16:33 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id B8697280024; Sat, 18 Feb 2023 16:16:33 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id A25D0280026; Sat, 18 Feb 2023 16:16:33 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id 8E409280024 for ; Sat, 18 Feb 2023 16:16:33 -0500 (EST) Received: from smtpin18.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay09.hostedemail.com (Postfix) with ESMTP id 644898058F for ; Sat, 18 Feb 2023 21:16:33 +0000 (UTC) X-FDA: 80481671466.18.A63C8ED Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by imf16.hostedemail.com (Postfix) with ESMTP id 3C72218000C for ; Sat, 18 Feb 2023 21:16:30 +0000 (UTC) Authentication-Results: imf16.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=DWblILRh; spf=pass (imf16.hostedemail.com: domain of rick.p.edgecombe@intel.com designates 192.55.52.43 as permitted sender) smtp.mailfrom=rick.p.edgecombe@intel.com; dmarc=pass (policy=none) header.from=intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1676754991; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references:dkim-signature; bh=08JkBkEO+Bx6wzCH5LqHBY8IMmstQr/gUoMXAKSYvwY=; b=1ifVeIFttissRks2ZB9DH4ZDysY5rI683KnQXWoXLuxGYOTyaVFYyZ0MFNzeaC6YNYukpd kMExEL+mi6OU7UChe42NhItSORYkpnDC7QXLT9xqwwpJ22h1PwVohavYgQ7/fUgjTS/Cxo tAWBBTWQkLl/4/z3Q/f1AZa/Ck8hEwo= ARC-Authentication-Results: i=1; imf16.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=DWblILRh; spf=pass (imf16.hostedemail.com: domain of rick.p.edgecombe@intel.com designates 192.55.52.43 as permitted sender) smtp.mailfrom=rick.p.edgecombe@intel.com; dmarc=pass (policy=none) header.from=intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1676754991; a=rsa-sha256; cv=none; b=Azm5Fj7xgufqrCreZjpPg+bGoLN0ZQSjJuDCcCYDMamPjLCCANHseKs7ZYJJ/oX74uovbe nQhxRl0N1QgR1UyArzM7sR9+Wx14Hj0JNgSFfW/Wg4gGfn90I52rbE/vZ6DZ4KNXX+8xc0 loEuLCbboL7ZYBvFRutLX5CcRbXYINU= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676754991; x=1708290991; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=xhLWZB/OZUOSeVyrlZfHv/Uy56frfc4dDYUp5qyh3D4=; b=DWblILRhqccTArLgMyIjbV3EtMMZncZEpEAkNvJC4qsAFpnT+xTVazKx oCVaLZxmXsjY3YojlvkOIKwh4L19Vupt4Cm4QHHj90AI8AssaiRaTeWmb DYr2/CJ+Ou2RT4uWFoCir9Tr1tIhh1shpRYKakIygmvrH39vF9YrWmgQK MmHX+9cfb+HAarldbZ8kNky+2Jch1+Nfkn5CvPXU1yW8Nvn1om60c7ITK K8xs6BQ3Ow1In1ZmIgVtjJayD1dlx94zv3qnSVWuDKGO9mZ9lEDhjO9a9 Lz4VzFDOhlWoyRU8nw74mVMBLV/QnI6rxpVOjbKdc0RpFDNHhzcht7eKf g==; X-IronPort-AV: E=McAfee;i="6500,9779,10625"; a="418427937" X-IronPort-AV: E=Sophos;i="5.97,309,1669104000"; d="scan'208";a="418427937" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2023 13:16:29 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10625"; a="664241760" X-IronPort-AV: E=Sophos;i="5.97,309,1669104000"; d="scan'208";a="664241760" Received: from adityava-mobl1.amr.corp.intel.com (HELO rpedgeco-desk.amr.corp.intel.com) ([10.209.80.223]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2023 13:16:28 -0800 From: Rick Edgecombe To: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , Weijiang Yang , "Kirill A . Shutemov" , John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, akpm@linux-foundation.org, Andrew.Cooper3@citrix.com, christina.schimpe@intel.com, david@redhat.com, debug@rivosinc.com Cc: rick.p.edgecombe@intel.com, Yu-cheng Yu Subject: [PATCH v6 39/41] x86: Add PTRACE interface for shadow stack Date: Sat, 18 Feb 2023 13:14:31 -0800 Message-Id: <20230218211433.26859-40-rick.p.edgecombe@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230218211433.26859-1-rick.p.edgecombe@intel.com> References: <20230218211433.26859-1-rick.p.edgecombe@intel.com> X-Rspamd-Queue-Id: 3C72218000C X-Stat-Signature: wscds18t1i7r8u4aoafmd4odcp1q5pau X-Rspam-User: X-Rspamd-Server: rspam08 X-HE-Tag: 1676754990-658039 X-HE-Meta: U2FsdGVkX1/XSYsyQzK4eGMZDfD5KlNerFFbiMkwHyCfpF3oxhSZYOLqwneMXGqfeQx1R5DhY8zqV23qavwmXeed3vMFgNBxginVRi/T51Cv9JTHxqk3WG4v9rBixsAjE/gN2Y+H5lIztIx4UlAMOmZO/hPpIXoVPD3bl7XcgYag1toXx8wQna4ST00/BWX2yR6uMG3fWjdb64ZfRwRsH0G0wNByAhOJ5ksis2q3WeXzy2XBaihr/LIlaMK7e9qPMFjhE0GiWsVhCdMWxAvKOimjodjYufFfPz1uVxg9rBvhKbZjTAAFq10cKM6KtikxErg8KzeyQrKP1osEBNi3BH/O0MY5aYaD7O0R4n0vsUBHzUO5z6PJe57gGANnDMEWfZDqXluGDYiD4PcQ7tKeOgygyDjfVT2/2d7NfmB/AXlkf7kJa8Nwx7oeR7tUPJ00N/QwwFZPPn/rIOsUeRUWsK//ofM1efcCDoyB1e+47ZTGXJBaM9tQ2adSMppZP4t+BP9CwRzKyRqdpEChURNvybMq/yczSS8fl1R3V+KgqGwnl4w6AF9CmiB+cxPSFPXNchAOaSDUxLGaIFuzQQ/b4zhpUQBr9+enDzXCQ3k4y2vg8XnTbI5mAo867sPt+F1CJngMOETBCoU7qGCIzABM31+9GHJpu2pTrvliftojepPx7+km/4h2mpLMWoUHmgWQ3d8NC6ab58ZqOoqo/okWBIUQn3+E1GaevtF6MUsS443ioLG62OqzN/LAE0NihhQrsYdrhS1xT64nBs1Dp8IYxm2O0G3lPNsBFBjhXXkGkG1N+TcMsiuUf0FAi3PL2tjve/5XH4gUlkdKDzLdciyIbGIOAcGZxWj/h7wDsKEeDSvK1tCQfa6Sk3VslXJlkPMyM+5wTH3IBdIfQa91XlvhwXI3uir03rLLqzU6OZg4tnqkC1AaHzB2DHNduYt4MFHUdZLcAIjv4HwkL8fdTKV nHhcGJif 7eBjcGE8JBgtKHhhtmJw85XNgyFaXE4VeyTtEu1fmIT/JDqjwJlAqL2yhia4HwWVaFKhsucMcbNV2bo7+oJTxalPYW2u6lYk6HTFigviTYuu42rdp/3B2s5SYmHS9nKWxBJTkhLWXZhs+0GGoC8bbEVpuDV3LGMUYBa/EmWS/GQB4sWMKgcO41Hw6bINQoEUHh/d7UIMXaO5fkBrznnpm9VLXaPOQdO6CaH1kca0mVw/FfzqpiC7vZnklkLi67PAdfCLvcdkht+QkR7b/8kccrjnpcSYSBQ1xMzGz X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Yu-cheng Yu Some applications (like GDB) would like to tweak shadow stack state via ptrace. This allows for existing functionality to continue to work for seized shadow stack applications. Provide an regset interface for manipulating the shadow stack pointer (SSP). There is already ptrace functionality for accessing xstate, but this does not include supervisor xfeatures. So there is not a completely clear place for where to put the shadow stack state. Adding it to the user xfeatures regset would complicate that code, as it currently shares logic with signals which should not have supervisor features. Don't add a general supervisor xfeature regset like the user one, because it is better to maintain flexibility for other supervisor xfeatures to define their own interface. For example, an xfeature may decide not to expose all of it's state to userspace, as is actually the case for shadow stack ptrace functionality. A lot of enum values remain to be used, so just put it in dedicated shadow stack regset. The only downside to not having a generic supervisor xfeature regset, is that apps need to be enlightened of any new supervisor xfeature exposed this way (i.e. they can't try to have generic save/restore logic). But maybe that is a good thing, because they have to think through each new xfeature instead of encountering issues when new a new supervisor xfeature was added. By adding a shadow stack regset, it also has the effect of including the shadow stack state in a core dump, which could be useful for debugging. The shadow stack specific xstate includes the SSP, and the shadow stack and WRSS enablement status. Enabling shadow stack or wrss in the kernel involves more than just flipping the bit. The kernel is made aware that it has to do extra things when cloning or handling signals. That logic is triggered off of separate feature enablement state kept in the task struct. So the flipping on HW shadow stack enforcement without notifying the kernel to change its behavior would severely limit what an application could do without crashing, and the results would depend on kernel internal implementation details. There is also no known use for controlling this state via prtace today. So only expose the SSP, which is something that userspace already has indirect control over. Tested-by: Pengfei Xu Tested-by: John Allen Reviewed-by: Kees Cook Co-developed-by: Rick Edgecombe Signed-off-by: Rick Edgecombe Signed-off-by: Yu-cheng Yu --- v5: - Check shadow stack enablement status for tracee (rppt) - Fix typo in comment v4: - Make shadow stack only. Reduce to only supporting SSP register, and remove CET references (peterz) - Add comment to not use 0x203, because binutils already looks for it in coredumps. (Christina Schimpe) v3: - Drop dependence on thread.shstk.size, and use thread.features bits - Drop 32 bit support v2: - Check alignment on ssp. - Block IBT bits. - Handle init states instead of returning error. - Add verbose commit log justifying the design. --- arch/x86/include/asm/fpu/regset.h | 7 +-- arch/x86/kernel/fpu/regset.c | 86 +++++++++++++++++++++++++++++++ arch/x86/kernel/ptrace.c | 12 +++++ include/uapi/linux/elf.h | 2 + 4 files changed, 104 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/fpu/regset.h b/arch/x86/include/asm/fpu/regset.h index 4f928d6a367b..697b77e96025 100644 --- a/arch/x86/include/asm/fpu/regset.h +++ b/arch/x86/include/asm/fpu/regset.h @@ -7,11 +7,12 @@ #include -extern user_regset_active_fn regset_fpregs_active, regset_xregset_fpregs_active; +extern user_regset_active_fn regset_fpregs_active, regset_xregset_fpregs_active, + ssp_active; extern user_regset_get2_fn fpregs_get, xfpregs_get, fpregs_soft_get, - xstateregs_get; + xstateregs_get, ssp_get; extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set, - xstateregs_set; + xstateregs_set, ssp_set; /* * xstateregs_active == regset_fpregs_active. Please refer to the comment diff --git a/arch/x86/kernel/fpu/regset.c b/arch/x86/kernel/fpu/regset.c index 6d056b68f4ed..c806952d9496 100644 --- a/arch/x86/kernel/fpu/regset.c +++ b/arch/x86/kernel/fpu/regset.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "context.h" #include "internal.h" @@ -174,6 +175,91 @@ int xstateregs_set(struct task_struct *target, const struct user_regset *regset, return ret; } +#ifdef CONFIG_X86_USER_SHADOW_STACK +int ssp_active(struct task_struct *target, const struct user_regset *regset) +{ + if (target->thread.features & ARCH_SHSTK_SHSTK) + return regset->n; + + return 0; +} + +int ssp_get(struct task_struct *target, const struct user_regset *regset, + struct membuf to) +{ + struct fpu *fpu = &target->thread.fpu; + struct cet_user_state *cetregs; + + if (!boot_cpu_has(X86_FEATURE_USER_SHSTK)) + return -ENODEV; + + sync_fpstate(fpu); + cetregs = get_xsave_addr(&fpu->fpstate->regs.xsave, XFEATURE_CET_USER); + if (!cetregs) { + /* + * The registers are the in the init state. The init values for + * these regs are zero, so just zero the output buffer. + */ + membuf_zero(&to, sizeof(cetregs->user_ssp)); + return 0; + } + + return membuf_write(&to, (unsigned long *)&cetregs->user_ssp, + sizeof(cetregs->user_ssp)); +} + +int ssp_set(struct task_struct *target, const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct fpu *fpu = &target->thread.fpu; + struct xregs_state *xsave = &fpu->fpstate->regs.xsave; + struct cet_user_state *cetregs; + unsigned long user_ssp; + int r; + + if (!boot_cpu_has(X86_FEATURE_USER_SHSTK) || + !ssp_active(target, regset)) + return -ENODEV; + + r = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &user_ssp, 0, -1); + if (r) + return r; + + /* + * Some kernel instructions (IRET, etc) can cause exceptions in the case + * of disallowed CET register values. Just prevent invalid values. + */ + if ((user_ssp >= TASK_SIZE_MAX) || !IS_ALIGNED(user_ssp, 8)) + return -EINVAL; + + fpu_force_restore(fpu); + + /* + * Don't want to init the xfeature until the kernel will definitely + * overwrite it, otherwise if it inits and then fails out, it would + * end up initing it to random data. + */ + if (!xfeature_saved(xsave, XFEATURE_CET_USER) && + WARN_ON(init_xfeature(xsave, XFEATURE_CET_USER))) + return -ENODEV; + + cetregs = get_xsave_addr(xsave, XFEATURE_CET_USER); + if (WARN_ON(!cetregs)) { + /* + * This shouldn't ever be NULL because it was successfully + * inited above if needed. The only scenario would be if an + * xfeature was somehow saved in a buffer, but not enabled in + * xsave. + */ + return -ENODEV; + } + + cetregs->user_ssp = user_ssp; + return 0; +} +#endif /* CONFIG_X86_USER_SHADOW_STACK */ + #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION /* diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c index dfaa270a7cc9..095f04bdabdc 100644 --- a/arch/x86/kernel/ptrace.c +++ b/arch/x86/kernel/ptrace.c @@ -58,6 +58,7 @@ enum x86_regset_64 { REGSET64_FP, REGSET64_IOPERM, REGSET64_XSTATE, + REGSET64_SSP, }; #define REGSET_GENERAL \ @@ -1267,6 +1268,17 @@ static struct user_regset x86_64_regsets[] __ro_after_init = { .active = ioperm_active, .regset_get = ioperm_get }, +#ifdef CONFIG_X86_USER_SHADOW_STACK + [REGSET64_SSP] = { + .core_note_type = NT_X86_SHSTK, + .n = 1, + .size = sizeof(u64), + .align = sizeof(u64), + .active = ssp_active, + .regset_get = ssp_get, + .set = ssp_set + }, +#endif }; static const struct user_regset_view user_x86_64_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 4c6a8fa5e7ed..413a15c07121 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -406,6 +406,8 @@ typedef struct elf64_shdr { #define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ #define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */ #define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */ +/* Old binutils treats 0x203 as a CET state */ +#define NT_X86_SHSTK 0x204 /* x86 SHSTK state */ #define NT_S390_HIGH_GPRS 0x300 /* s390 upper register halves */ #define NT_S390_TIMER 0x301 /* s390 timer register */ #define NT_S390_TODCMP 0x302 /* s390 TOD clock comparator register */