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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Feb 2023 18:50:53.3995 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d92763a-4afd-4cd0-86c0-08db137364b4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8129 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 397068001E X-Stat-Signature: kid7ymprb8tqrt6zgs9rwptjgc6r37hy X-Rspam-User: X-HE-Tag: 1676919056-872615 X-HE-Meta: U2FsdGVkX1+E+MdOJqXhLT+FkYOpoEPAMu9afuuHEeGV4Hu79acNuw5AhZClgHFHdwS+M+faOlVzKX8hKMJD07gEAKgLNKwy4AEjSfxMVHZfbz75G631ppBW25y7MvM8MzUAN2JFErHZpZI3VrBIuAW0gkk5jyWftK1jXo0gvNN9aCRwY6kkTRIJclfV+WYLucqo8RLSYXbMtVdngnBv/OuPxx4DmXiTwGy1S9w0ZvcDHeBpMi0PWF0CjuWssD7a6xPR/54ufLW1SPysH1QuYu1OGy9RqiP1vzkGNEdiQOufsUcJ/6V425mp1F82zZE3vRK2Nvpu6YqtC6WQhV8hbsw5S0j9fCtZMv8YlOxcQIGIun+a2yxkc1tV/oJhxFoYCybwDGHJMth8YEpGZMPBBam89jve0Wdzit+81E6A9rz7eJb4sI74PKiJj2HfkoZn4HSaxf72x8IjVZMaF9HpNgZ+1ukXAEvGF5N40Fztm4jePyhVmRU6sLKl9sLZANj2lcTHjMk5xAcKAZhe6HMpQY0g+lxoc+B1W7yUMYN7yqFXEJYfTx1CeAv5hHfOY4kr3Vcjd/GJ0Vi7mYhrPftJiIAZgdtSu9BbVm3zYqocus5KW1BANCHmQTTUk4NmHWjSh+1aN/hqY+Aaef5z8vzhj8bOySSWRi4xv7TgT4fzqEzACn0kXUAA3s7CWc3n/4EPV1cwVqwOnHB34Z/hvipTc/hQeISsq29U0I1ZzqNlpoXZCznFVQ1aoldQ8sih2YznWMI4A/28esEEtXGOSCEKVSSm9Yc8IT64ONpUrGp2decsN5f08UZc40SsDKYD+Gis8bs71KJU9dXhxupbXy3QhKhmHXnQk1HLzyj7/VlnQPx3XECrXgqHcEbKINRFriCZuBtZzRiaWi+uFIjDsKPn/I1nOI6jKfR55Wd8hA+94/SsMx0nLiHCBJUZPd/VSTCTrX4glq9xC/yz5ep67nj 8LmKYgHy uPZZd48Ca8jA44ikwXzTxrQ1YYZQVnvWm8UGI0krxxaK6fDl+laQuAuhzReItTgJdtK3j/C8/b50yMPoY+P3aXVrl4J+YdzIYnz1pi2Rpw0cA4emnGX6P1Ee9SOlfNmgpTv17tzkw2rQkS+n0XxRjrQWMl4m46QNGYUmNUyxJdqwOWumBs1H5dgU4MbOGE0yDdW7b/VQpTE6WRJiHvkIrhQjIyyT9KjbjtztV+rEfzjSV3FDKomPv8mAjoACteU9q+0A5c3EQ0gELdSlUd0ZnloyZfrSYTjgXH//9XLAPUKvFhDQWBGQwdXAmj8Xb6XkknfcuSZZNe/Njrg4= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Tom Lendacky Add support for AP Reset Hold being invoked using the GHCB MSR protocol, available in version 2 of the GHCB specification. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra Signed-off-by: Michael Roth --- arch/x86/include/asm/sev-common.h | 2 ++ arch/x86/kvm/svm/sev.c | 56 ++++++++++++++++++++++++++----- arch/x86/kvm/svm/svm.h | 1 + 3 files changed, 51 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index b8357d6ecd47..e15548d88f2a 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -56,6 +56,8 @@ /* AP Reset Hold */ #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) /* GHCB GPA Register */ #define GHCB_MSR_REG_GPA_REQ 0x012 diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index ad9b29ff4590..05eda0940e22 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -58,6 +58,10 @@ module_param_named(sev_es, sev_es_enabled, bool, 0444); #define sev_es_enabled false #endif /* CONFIG_KVM_AMD_SEV */ +#define AP_RESET_HOLD_NONE 0 +#define AP_RESET_HOLD_NAE_EVENT 1 +#define AP_RESET_HOLD_MSR_PROTO 2 + static u8 sev_enc_bit; static DECLARE_RWSEM(sev_deactivate_lock); static DEFINE_MUTEX(sev_bitmap_lock); @@ -2706,6 +2710,9 @@ static int sev_es_validate_vmgexit(struct vcpu_svm *svm) void sev_es_unmap_ghcb(struct vcpu_svm *svm) { + /* Clear any indication that the vCPU is in a type of AP Reset Hold */ + svm->sev_es.ap_reset_hold_type = AP_RESET_HOLD_NONE; + if (!svm->sev_es.ghcb) return; @@ -2918,6 +2925,22 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) GHCB_MSR_INFO_POS); break; } + case GHCB_MSR_AP_RESET_HOLD_REQ: + svm->sev_es.ap_reset_hold_type = AP_RESET_HOLD_MSR_PROTO; + ret = kvm_emulate_ap_reset_hold(&svm->vcpu); + + /* + * Preset the result to a non-SIPI return and then only set + * the result to non-zero when delivering a SIPI. + */ + set_ghcb_msr_bits(svm, 0, + GHCB_MSR_AP_RESET_HOLD_RESULT_MASK, + GHCB_MSR_AP_RESET_HOLD_RESULT_POS); + + set_ghcb_msr_bits(svm, GHCB_MSR_AP_RESET_HOLD_RESP, + GHCB_MSR_INFO_MASK, + GHCB_MSR_INFO_POS); + break; case GHCB_MSR_TERM_REQ: { u64 reason_set, reason_code; @@ -3017,6 +3040,7 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu) ret = svm_invoke_exit_handler(vcpu, SVM_EXIT_IRET); break; case SVM_VMGEXIT_AP_HLT_LOOP: + svm->sev_es.ap_reset_hold_type = AP_RESET_HOLD_NAE_EVENT; ret = kvm_emulate_ap_reset_hold(vcpu); break; case SVM_VMGEXIT_AP_JUMP_TABLE: { @@ -3177,13 +3201,29 @@ void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) return; } - /* - * Subsequent SIPI: Return from an AP Reset Hold VMGEXIT, where - * the guest will set the CS and RIP. Set SW_EXIT_INFO_2 to a - * non-zero value. - */ - if (!svm->sev_es.ghcb) - return; + /* Subsequent SIPI */ + switch (svm->sev_es.ap_reset_hold_type) { + case AP_RESET_HOLD_NAE_EVENT: + /* + * Return from an AP Reset Hold VMGEXIT, where the guest will + * set the CS and RIP. Set SW_EXIT_INFO_2 to a non-zero value. + */ + ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, 1); + break; + case AP_RESET_HOLD_MSR_PROTO: + /* + * Return from an AP Reset Hold VMGEXIT, where the guest will + * set the CS and RIP. Set GHCB data field to a non-zero value. + */ + set_ghcb_msr_bits(svm, 1, + GHCB_MSR_AP_RESET_HOLD_RESULT_MASK, + GHCB_MSR_AP_RESET_HOLD_RESULT_POS); - ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, 1); + set_ghcb_msr_bits(svm, GHCB_MSR_AP_RESET_HOLD_RESP, + GHCB_MSR_INFO_MASK, + GHCB_MSR_INFO_POS); + break; + default: + break; + } } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 56e306a1f0c7..f4848e6aba28 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -191,6 +191,7 @@ struct vcpu_sev_es_state { struct ghcb *ghcb; struct kvm_host_map ghcb_map; bool received_first_sipi; + unsigned int ap_reset_hold_type; /* SEV-ES scratch area support */ void *ghcb_sa;