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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF000108EA.mail.protection.outlook.com (10.167.241.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6134.14 via Frontend Transport; Mon, 20 Feb 2023 18:55:47 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 20 Feb 2023 12:55:46 -0600 From: Michael Roth To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Brijesh Singh Subject: [PATCH RFC v8 41/56] KVM: SVM: Add support to handle MSR based Page State Change VMGEXIT Date: Mon, 20 Feb 2023 12:38:32 -0600 Message-ID: <20230220183847.59159-42-michael.roth@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220183847.59159-1-michael.roth@amd.com> References: <20230220183847.59159-1-michael.roth@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108EA:EE_|BL1PR12MB5063:EE_ X-MS-Office365-Filtering-Correlation-Id: fbf6540a-1c30-43b7-58a6-08db137413d3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Feb 2023 18:55:47.1715 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fbf6540a-1c30-43b7-58a6-08db137413d3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5063 X-Rspam-User: X-Rspamd-Server: rspam03 X-Stat-Signature: zp7etddpnajk9uob6dbxa9jed6frjjqp X-Rspamd-Queue-Id: 47F5110000C X-HE-Tag: 1676919350-92464 X-HE-Meta: U2FsdGVkX1/RedMrci7lQ6/FRbS3sB4PFtP3KSxnj+Yg7NpPTjYG5pKtyJ1nud853cNmRMODvGFohWZQOs6BG5XpuxGoWOyntbuZfJGr3WdPY5ZqSPo7yfsQmaks2DCGR/0wnTeSu2MFu743ZBEfpi3weVpDTauEiLQW2H72enpKNr0dfPt1Ry3FYgs+n1gOKodoobcYxS6SlfFkuQ9uLPdi1HvBpXs7fa4IdnMsKk4VYFhKXK5GDors6yKkr22aY+HtZ9xcHOclmsehYx5cqCFGcNgdmU+nZR9O5OSoeB658CSyU9ppYaXCIHlCsWXSCBOvVVf2o9faGE5em3txdw8xdEPDu74ql0eDcd83e8kki+wy4TF2K5cLguNh2cKkA9khtfj2WjYLhzs7A963TKE+RX6n7AJnldnGskcwsGTPq7ZxfTN9yJMxYKSISWyvoHou6R2mNMzNmKcX6zI+6sn1/v81N2UPiGCFvuTuEgDDW9BNRT+6B7KO231+WsedB3BivDZkcOA9FvwS0xEatfDg7LRJ3i96JFn1s4hLy3uakPtPzcaJjPX0JdnE58ZhcgVacKtXry3e2/qT5YdCG+bUOgjVPd8iS10rcknCMs93c/wIMOoZOa4xE2BJyx52XAIssnJwRThjc4EhOemVBaBzPqe4iO2ye4LBlYl6C/QHIk4YLLZHCk3gLQ42VXsvguPnc6IQELSFR6/fPYUfQNkg1wK8Hd58gDERJwiTLCUrt9qhndQNLOnqmpYrbPmGw2Bbn8OwFhZMDdwpdgj6mi8ks+idJ6i+gdyQEkWP2nu2inKvDqmfrvrNi/RfH0CiMeO9AwrO62/JGMjZUR7u8ID+YBMJ5OXyHkLZ++0x0+C8QTLaaV7QlqZEVpjRMi/Y8kUhLsm/LUysJD1mxi+W8rWmO74bRnby4dcUAsnw96NyLicexPFDGycNqp1SCviy0eSUHIgsZAkFD7vGGoA 52LhKiF1 oS3uv48KlJTEpLgV+BZUpZ1fPATbxSj133oUVi4AqRWxDwYXJmZJGphUY5dwR86cWaohW1EJ74MGnBrkwyC5H+i3iXEzqn8JJSj6nlGQXvW9CcTSea+EPX8xy+5Sg4xoOdWtZKSSm66VDSoyrS0NbdFUZnLmAU7pqUAutdqjKYukDrjJPV8rlLXMyQ6Ktq3tpv1i8lZhQ0lzpGDHLZauFBI7XSOW4C+V7LpAm7lCb7u/vC9BmTYtApS9npIAiGuXSB20x2eJ10STtkL36CJ1nQwDblrlp+ufzfxidmQoiDZsEQPlI1keSAdkVa6KJxZkFiD3oirSO2ONrrRo= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Brijesh Singh SEV-SNP VMs can ask the hypervisor to change the page state in the RMP table to be private or shared using the Page State Change MSR protocol as defined in the GHCB specification. Forward these requests to userspace via KVM_EXIT_VMGEXIT so the VMM can issue the KVM ioctls to update the page state accordingly. Co-developed-by: Michael Roth Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra --- arch/x86/include/asm/sev-common.h | 9 ++++++++ arch/x86/kvm/svm/sev.c | 25 +++++++++++++++++++++++ arch/x86/kvm/trace.h | 34 +++++++++++++++++++++++++++++++ arch/x86/kvm/x86.c | 1 + 4 files changed, 69 insertions(+) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 0a9055cdfae2..ee38f7408470 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -93,6 +93,10 @@ enum psc_op { }; #define GHCB_MSR_PSC_REQ 0x014 +#define GHCB_MSR_PSC_GFN_POS 12 +#define GHCB_MSR_PSC_GFN_MASK GENMASK_ULL(39, 0) +#define GHCB_MSR_PSC_OP_POS 52 +#define GHCB_MSR_PSC_OP_MASK 0xf #define GHCB_MSR_PSC_REQ_GFN(gfn, op) \ /* GHCBData[55:52] */ \ (((u64)((op) & 0xf) << 52) | \ @@ -102,6 +106,11 @@ enum psc_op { GHCB_MSR_PSC_REQ) #define GHCB_MSR_PSC_RESP 0x015 +#define GHCB_MSR_PSC_ERROR_POS 32 +#define GHCB_MSR_PSC_ERROR_MASK GENMASK_ULL(31, 0) +#define GHCB_MSR_PSC_ERROR GENMASK_ULL(31, 0) +#define GHCB_MSR_PSC_RSVD_POS 12 +#define GHCB_MSR_PSC_RSVD_MASK GENMASK_ULL(19, 0) #define GHCB_MSR_PSC_RESP_VAL(val) \ /* GHCBData[63:32] */ \ (((u64)(val) & GENMASK_ULL(63, 32)) >> 32) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 2613311f4fcc..a1a2686dde7b 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -30,6 +30,7 @@ #include "svm_ops.h" #include "cpuid.h" #include "trace.h" +#include "mmu.h" #ifndef CONFIG_KVM_AMD_SEV /* @@ -3345,6 +3346,23 @@ static void set_ghcb_msr(struct vcpu_svm *svm, u64 value) svm->vmcb->control.ghcb_gpa = value; } +/* + * TODO: need to get the value set by userspace in vcpu->run->vmgexit.ghcb_msr + * and process that here accordingly. + */ +static int snp_complete_psc_msr_protocol(struct kvm_vcpu *vcpu) +{ + struct vcpu_svm *svm = to_svm(vcpu); + + set_ghcb_msr_bits(svm, 0, + GHCB_MSR_PSC_ERROR_MASK, GHCB_MSR_PSC_ERROR_POS); + + set_ghcb_msr_bits(svm, 0, GHCB_MSR_PSC_RSVD_MASK, GHCB_MSR_PSC_RSVD_POS); + set_ghcb_msr_bits(svm, GHCB_MSR_PSC_RESP, GHCB_MSR_INFO_MASK, GHCB_MSR_INFO_POS); + + return 1; /* resume */ +} + static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) { struct vmcb_control_area *control = &svm->vmcb->control; @@ -3445,6 +3463,13 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) GHCB_MSR_INFO_POS); break; } + case GHCB_MSR_PSC_REQ: + vcpu->run->exit_reason = KVM_EXIT_VMGEXIT; + vcpu->run->vmgexit.ghcb_msr = control->ghcb_gpa; + vcpu->arch.complete_userspace_io = snp_complete_psc_msr_protocol; + + ret = -1; + break; case GHCB_MSR_TERM_REQ: { u64 reason_set, reason_code; diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index 83843379813e..65861d2d086c 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h @@ -7,6 +7,7 @@ #include #include #include +#include #undef TRACE_SYSTEM #define TRACE_SYSTEM kvm @@ -1831,6 +1832,39 @@ TRACE_EVENT(kvm_vmgexit_msr_protocol_exit, __entry->vcpu_id, __entry->ghcb_gpa, __entry->result) ); +/* + * Tracepoint for the SEV-SNP page state change processing + */ +#define psc_operation \ + {SNP_PAGE_STATE_PRIVATE, "private"}, \ + {SNP_PAGE_STATE_SHARED, "shared"} \ + +TRACE_EVENT(kvm_snp_psc, + TP_PROTO(unsigned int vcpu_id, u64 pfn, u64 gpa, u8 op, int level), + TP_ARGS(vcpu_id, pfn, gpa, op, level), + + TP_STRUCT__entry( + __field(int, vcpu_id) + __field(u64, pfn) + __field(u64, gpa) + __field(u8, op) + __field(int, level) + ), + + TP_fast_assign( + __entry->vcpu_id = vcpu_id; + __entry->pfn = pfn; + __entry->gpa = gpa; + __entry->op = op; + __entry->level = level; + ), + + TP_printk("vcpu %u, pfn %llx, gpa %llx, op %s, level %d", + __entry->vcpu_id, __entry->pfn, __entry->gpa, + __print_symbolic(__entry->op, psc_operation), + __entry->level) +); + #endif /* _TRACE_KVM_H */ #undef TRACE_INCLUDE_PATH diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 268c3d16894d..0154fc7a28c1 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13515,6 +13515,7 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); +EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_snp_psc); static int __init kvm_x86_init(void) {