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Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , Linus Torvalds , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv16 03/17] x86: CPUID and CR3/CR4 flags for Linear Address Masking Date: Sun, 12 Mar 2023 14:25:58 +0300 Message-Id: <20230312112612.31869-4-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230312112612.31869-1-kirill.shutemov@linux.intel.com> References: <20230312112612.31869-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam03 X-Stat-Signature: k7xhsmqxcfhz3zue3t3knu77g6yiipaa X-Rspamd-Queue-Id: 3BA57C0014 X-HE-Tag: 1678620390-212078 X-HE-Meta: U2FsdGVkX19lNXAD1X7HCePjEU+e2O0QrHh7sJ1pijy7Ok8vkQ3L9tNOvSEHvMDsck6RJaNEOkDwKqlk8BIS380sQSPCP9p8qAvCV4Lwh+MT6W0TOJMi15EnFKaZoRepfqjzzb4PJxf3L1Oq6lD7iJ27AFrRRDz5f0me/iyrGE7v6isEApp392ETu8gATOf+ZbcR15uWWPliHp7vW+e0Rs++RPqSNoywPut0Sy3oes9Klpo/u4G7tYnYBWFPJr2qCEbe0s+7kEBqa00pMVLt9mds1R93OYkPsr/sj7wbnmj/ZgMjXT+bFZNU50rpp5NzlhloNb/zJa3NnChkxn6rYHAcyB/p4Txj6UBSSwwokvJ5Fgs/XlOLETwExZYTt5lHyqt4Dx/0/FDS42Lz44q/zftL94J+TU5J5ENtytgAoOjK7bq1LcfhbY45PxzlQeEO5fEk0hSVg48Np3WR2n7/0eKL/6iO7HaEeqK6O4CDxcTI0iYRmVtecFcelpX+p/tSLW02chfxEb5r0KvZVTOj+kKVsUukdUiVsg+IGYdIAjUT1cYXbESNO8BLT/tcCTaE5jBif/41udyEtzUPAre+UilT26XQty1tGObObRIkmgLLKXlaxep0SlCXe9aaEWHHm7bYrwHxWvZJ6cXbhVro7sGYHi6ZdK8av9i8ocEC4dZAulh4ljqvtl0i1UZsvzjt+rQU1MUQc4RGUtKCvu+ymO3O+L/cZdBYwsylZA2SnRp9BsWEfpfaTD3LY847AlZH3xF1OrvAb/8jeSAI6F6KELZ5GLTmVnrOBSfehJaY8nlEDH/85MoNoJ5PzKnm1jBeDe4XncvffYb65+vkBOlrL302J0EB/d+V5u87tQggmEQ1W8aXJECIUVY6xGBd6vpUE1kK4zKyrLg9pv9Fugx4YQNlg2Hu1jCvx20drUpBWIPZQRMpcfYL/mQEbnlKAp3O0WzZOxd2qCovsgBLm4I 4tqfQch8 UqXj7ke7dRLpsAg6nUhxmtTugvlWnWNcLbHnNRIu9YUNBftJjN/w2MVsVzGusQFmAyJj7vobuMVHJwcw1+WVhdoLwDQCEtHG+Wfnq9bMTQZ2txAep0c2ymGhzVFTxIo9V0Ivp+67MWvkM3SHbBIKfaJj14rIduvwkNDnS54GBKvCSIXTVO3mmBXfsNK937ED4z9IHhcqvW7jh0ljOp3SjibosP9/KkKV1Hkyp1kpoluUe+MEzCbmR0pJhEJPJRd+CkyHXG6kN2EoCEZKmes0Y7CAeAjkSK8cHQy0/e255aKJ8rjBvA8QRulPw8t4VNH6iyarMMJZoMwTKRm6H8Aalf+XFgcHJqUBdL6fzJ4SsDWilgKg= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Enumerate Linear Address Masking and provide defines for CR3 and CR4 flags. The new CONFIG_ADDRESS_MASKING option enables the feature support in kernel. Signed-off-by: Kirill A. Shutemov Reviewed-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) Tested-by: Alexander Potapenko --- arch/x86/Kconfig | 11 +++++++++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/processor-flags.h | 2 ++ arch/x86/include/uapi/asm/processor-flags.h | 6 ++++++ 4 files changed, 20 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a825bf031f49..aa9f73f5d670 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2290,6 +2290,17 @@ config RANDOMIZE_MEMORY_PHYSICAL_PADDING If unsure, leave at the default value. +config ADDRESS_MASKING + bool "Linear Address Masking support" + depends on X86_64 + help + Linear Address Masking (LAM) modifies the checking that is applied + to 64-bit linear addresses, allowing software to use of the + untranslated address bits for metadata. + + The capability can be used for efficient address sanitizers (ASAN) + implementation and for optimizations in JITs. + config HOTPLUG_CPU def_bool y depends on SMP diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 73c9672c123b..353b054812de 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -321,6 +321,7 @@ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ +#define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index a7f3d9100adb..d8cccadc83a6 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -28,6 +28,8 @@ * On systems with SME, one bit (in a variable position!) is stolen to indicate * that the top-level paging structure is encrypted. * + * On systemms with LAM, bits 61 and 62 are used to indicate LAM mode. + * * All of the remaining bits indicate the physical address of the top-level * paging structure. * diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index c47cc7f2feeb..d898432947ff 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -82,6 +82,10 @@ #define X86_CR3_PCID_BITS 12 #define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL)) +#define X86_CR3_LAM_U57_BIT 61 /* Activate LAM for userspace, 62:57 bits masked */ +#define X86_CR3_LAM_U57 _BITULL(X86_CR3_LAM_U57_BIT) +#define X86_CR3_LAM_U48_BIT 62 /* Activate LAM for userspace, 62:48 bits masked */ +#define X86_CR3_LAM_U48 _BITULL(X86_CR3_LAM_U48_BIT) #define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */ #define X86_CR3_PCID_NOFLUSH _BITULL(X86_CR3_PCID_NOFLUSH_BIT) @@ -132,6 +136,8 @@ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) #define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology */ #define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) +#define X86_CR4_LAM_SUP_BIT 28 /* LAM for supervisor pointers */ +#define X86_CR4_LAM_SUP _BITUL(X86_CR4_LAM_SUP_BIT) /* * x86-64 Task Priority Register, CR8