From patchwork Sun Mar 19 00:14:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgecombe, Rick P" X-Patchwork-Id: 13180128 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41E01C7618A for ; Sun, 19 Mar 2023 00:16:01 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 442DB900003; Sat, 18 Mar 2023 20:16:00 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 3CB97900002; Sat, 18 Mar 2023 20:16:00 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 24594900003; Sat, 18 Mar 2023 20:16:00 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0014.hostedemail.com [216.40.44.14]) by kanga.kvack.org (Postfix) with ESMTP id 0EE47900002 for ; Sat, 18 Mar 2023 20:16:00 -0400 (EDT) Received: from smtpin23.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay02.hostedemail.com (Postfix) with ESMTP id C933A120C71 for ; Sun, 19 Mar 2023 00:15:59 +0000 (UTC) X-FDA: 80583730038.23.4CBB0A3 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by imf07.hostedemail.com (Postfix) with ESMTP id A533240013 for ; Sun, 19 Mar 2023 00:15:57 +0000 (UTC) Authentication-Results: imf07.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=GubkTHeS; spf=pass (imf07.hostedemail.com: domain of rick.p.edgecombe@intel.com designates 192.55.52.115 as permitted sender) smtp.mailfrom=rick.p.edgecombe@intel.com; dmarc=pass (policy=none) header.from=intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1679184958; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references:dkim-signature; bh=zRxHGq/x4fwbwwr5Ekrd9FyaMCugduAsObDIjvFXmzA=; b=i87yAcgrZZbPl/bJJlClftftFQXlJp6TXeyPRO+fKR4SAeLjulyKHfo8KheXReetM3ETpH QzZLlWDit31DFQNolv4oA6JA/IEUc0FBLZgy3QWNrSHRTkhBsxYyC/bpbRPNuA8bncVpBP vcK88qhb6PjBrFzEwfmoJ9JC6rEXkQA= ARC-Authentication-Results: i=1; imf07.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=GubkTHeS; spf=pass (imf07.hostedemail.com: domain of rick.p.edgecombe@intel.com designates 192.55.52.115 as permitted sender) smtp.mailfrom=rick.p.edgecombe@intel.com; dmarc=pass (policy=none) header.from=intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1679184958; a=rsa-sha256; cv=none; b=3FZik2Yw2qn9s9LAnzdsGFNV/nfkhvOKlZDhb1FxMwdU82bKQa0prJT0Ih4YbVp+tM0tTT p+j0qGXFGKcDAVhkhmK1iuIqLSeyAv3aot43Lmro0GXQYHqjQyaz1EUwbKouK0WOD4XUIE 0pCrsocj1cK2HbouiW15hWZf97nknlo= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679184957; x=1710720957; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=0t92Iyq66UV7JVrVlXJ2Eu9M0Ep1BbamDrvvLE4ZT7Y=; b=GubkTHeScrUhwfbViH/zm3mLYHaCsg+wFARcj5uv2jyeKwWxFOkdrVPN k515uQcels/JkQH7l3jQLXyPmxSeYjv92XhvXuKmhASjVA2aTn8XTqTWs l+Fxktuwg7McKXg2ONnnVNZ5UpIztK2YSmgod+J7HvL2dOSF9jG1SD03y GN44D6wnXUkqlqWUfnQfx2VcsWltkJeh2IjEn495JCpJfussNj1XRKI/R hiN+Bhf6m6oI2S2Y9BJt1zJgZMhBDEcCUm1A2uDawVWWkViA8jukhz3Ur yJQt8rfxCCgdeNtUpwGgLFgUmbT+ZTSQmsRWZm+CjRvQ8bW0iHMUG3w5c g==; X-IronPort-AV: E=McAfee;i="6600,9927,10653"; a="338490746" X-IronPort-AV: E=Sophos;i="5.98,272,1673942400"; d="scan'208";a="338490746" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2023 17:15:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10653"; a="749672767" X-IronPort-AV: E=Sophos;i="5.98,272,1673942400"; d="scan'208";a="749672767" Received: from bmahatwo-mobl1.gar.corp.intel.com (HELO rpedgeco-desk.amr.corp.intel.com) ([10.135.34.5]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2023 17:15:54 -0700 From: Rick Edgecombe To: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , Weijiang Yang , "Kirill A . Shutemov" , John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, akpm@linux-foundation.org, Andrew.Cooper3@citrix.com, christina.schimpe@intel.com, david@redhat.com, debug@rivosinc.com, szabolcs.nagy@arm.com Cc: rick.p.edgecombe@intel.com, Yu-cheng Yu Subject: [PATCH v8 01/40] Documentation/x86: Add CET shadow stack description Date: Sat, 18 Mar 2023 17:14:56 -0700 Message-Id: <20230319001535.23210-2-rick.p.edgecombe@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230319001535.23210-1-rick.p.edgecombe@intel.com> References: <20230319001535.23210-1-rick.p.edgecombe@intel.com> X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: A533240013 X-Stat-Signature: hz91waqazr1bkdapr4tb3asj14pune4g X-Rspam-User: X-HE-Tag: 1679184957-131326 X-HE-Meta: U2FsdGVkX1/A7rVhtPoBtPDxVEKKSK+KXYJi80DrXzyOIhS3XQ5zmjnkNrO6DuxiLVTHT5Bcqhz41WDGt+cMUzIvbqrT5oDGhdy16OS+5F3bOcjbvMueyzDTq5lGNZVu11kOj1uSExQ5CCjcIHJUmjSX0knGcT1AYLnqxaw4K8HY9a07egnfeDERDdAxtfK0Ompz5P0EWUvWHBMpNkmD4qYV+tLt3wiUWsFney6KIxHZcpmWEkNLGCIz4XDgk+iMmnZIAP6qDq4E7ODnPEbxzgSXQa0DtIIy3oyTv6rU1hb48WAcCXkgOA3X3SfXBWKehOb9EkVWKBC0kNq72lsAkGqGaJ4hVup+NoWntrDl9aUOYfS9I0khlY7mJu2yz+qfg8q0eNI3cCHjtK/YC7ye/QeaCZJwtduCWxBV2npIzg1qKwmHtMuogmMLzr1L1ekangmbTGalrJh4ac9E9ej7hUHse+dz6+MQkXhUmOutdBIUo/tYT3aQE/RutB0YPIOKkB1z76K5MZDxGwLFGZsP/XY2OAb99Tb6riAKXBK4GtdQgWIYtovyWlYzPqtAcFIvKmXV3hBSkenszr7z8WDj6PaDX4dUl/k+6nBQKUJ7f1eZvPCoZvwJxbMa5aiKZO11g9B4DSVkeTL/XlgTIBzwz+dgP49UZfXYmrR5LHytymNNmyC5TlGU+gLHpkQ9pF4CvlI4XsT5S+OLQI4F56RpK9cwxEcuyinZWyeZVvF8UdF+0gcEBWplzQwaL/GH6hV37kuNr3X1wdRpwb5dK5aYUY94YmnExAAV26zb8qrbDhI5BP3sj4PikPXRILgppR124jzSzvqeJ6Q8FtRo0XYa2yGyquSnyLpvjOSV3lyKL6QXZpu+8EVnIkdefHRd/F6EbN9qsBZN8mmwjrXGFXffooTbECLwM/lK+kO0DZomvLoTvTW6QFzgsSapIoznS5nfF8d/wNhEXnA8bz2Ik6G cL8EAnRT 7JFi39oL5ibI/rzVSzcW0tavnAOHZ8i/IH/k9e8tpcvGptgPf/2KeCvjP7phDVtVFkbsrsTdPsQrrjkfOogH/5ihzKMJSCL0quYctrNOZ0V4f0FKuVWqIvi3XSdVIphwXejhqVtsw9sg8+xApqk7c6ZAJ/XnexIlxnfWmc4wpvvNr34EGk9b9kRKWDS2KRS2LmPUZRW+WK1gOGVY46R7ObQWJgMAACMlxqH7mp9xBIdNruAYC9H6inup2aWsiUOdEePIsS1/Zb1fDjinfgZTEoSfuEyiPZpe7yuBe33GAMMbhUZrdXeNeO/ctHRk8hrC4aPWgM9Hk8o3RgbQlCXQ9SqNk+stcxxnIouGD X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Introduce a new document on Control-flow Enforcement Technology (CET). Co-developed-by: Yu-cheng Yu Signed-off-by: Yu-cheng Yu Signed-off-by: Rick Edgecombe Reviewed-by: Kees Cook Acked-by: Mike Rapoport (IBM) Tested-by: Pengfei Xu Tested-by: John Allen Tested-by: Kees Cook --- v8: - Add more details to docs (Szabolcs Nagy) - More doc tweaks (Dave Hansen) v5: - Literal format tweaks (Bagas Sanjaya) - Update EOPNOTSUPP text due to unification after comment from (Kees) - Update 32 bit signal support with new behavior - Remove capitalization on shadow stack (Boris) - Fix typo v4: - Drop clearcpuid piece (Boris) - Add some info about 32 bit v3: - Clarify kernel IBT is supported by the kernel. (Kees, Andrew Cooper) - Clarify which arch_prctl's can take multiple bits. (Kees) - Describe ASLR characteristics of thread shadow stacks. (Kees) - Add exec section. (Andrew Cooper) - Fix some capitalization (Bagas Sanjaya) - Update new location of enablement status proc. - Add info about new user_shstk software capability. - Add more info about what the kernel pushes to the shadow stack on signal. --- Documentation/x86/index.rst | 1 + Documentation/x86/shstk.rst | 169 ++++++++++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+) create mode 100644 Documentation/x86/shstk.rst diff --git a/Documentation/x86/index.rst b/Documentation/x86/index.rst index c73d133fd37c..8ac64d7de4dc 100644 --- a/Documentation/x86/index.rst +++ b/Documentation/x86/index.rst @@ -22,6 +22,7 @@ x86-specific Documentation mtrr pat intel-hfi + shstk iommu intel_txt amd-memory-encryption diff --git a/Documentation/x86/shstk.rst b/Documentation/x86/shstk.rst new file mode 100644 index 000000000000..f09afa504ec0 --- /dev/null +++ b/Documentation/x86/shstk.rst @@ -0,0 +1,169 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================================== +Control-flow Enforcement Technology (CET) Shadow Stack +====================================================== + +CET Background +============== + +Control-flow Enforcement Technology (CET) covers several related x86 processor +features that provide protection against control flow hijacking attacks. CET +can protect both applications and the kernel. + +CET introduces shadow stack and indirect branch tracking (IBT). A shadow stack +is a secondary stack allocated from memory which cannot be directly modified by +applications. When executing a CALL instruction, the processor pushes the +return address to both the normal stack and the shadow stack. Upon +function return, the processor pops the shadow stack copy and compares it +to the normal stack copy. If the two differ, the processor raises a +control-protection fault. IBT verifies indirect CALL/JMP targets are intended +as marked by the compiler with 'ENDBR' opcodes. Not all CPU's have both Shadow +Stack and Indirect Branch Tracking. Today in the 64-bit kernel, only userspace +shadow stack and kernel IBT are supported. + +Requirements to use Shadow Stack +================================ + +To use userspace shadow stack you need HW that supports it, a kernel +configured with it and userspace libraries compiled with it. + +The kernel Kconfig option is X86_USER_SHADOW_STACK. When compiled in, shadow +stacks can be disabled at runtime with the kernel parameter: nousershstk. + +To build a user shadow stack enabled kernel, Binutils v2.29 or LLVM v6 or later +are required. + +At run time, /proc/cpuinfo shows CET features if the processor supports +CET. "user_shstk" means that userspace shadow stack is supported on the current +kernel and HW. + +Application Enabling +==================== + +An application's CET capability is marked in its ELF note and can be verified +from readelf/llvm-readelf output:: + + readelf -n | grep -a SHSTK + properties: x86 feature: SHSTK + +The kernel does not process these applications markers directly. Applications +or loaders must enable CET features using the interface described in section 4. +Typically this would be done in dynamic loader or static runtime objects, as is +the case in GLIBC. + +Enabling arch_prctl()'s +======================= + +Elf features should be enabled by the loader using the below arch_prctl's. They +are only supported in 64 bit user applications. These operate on the features +on a per-thread basis. The enablement status is inherited on clone, so if the +feature is enabled on the first thread, it will propagate to all the thread's +in an app. + +arch_prctl(ARCH_SHSTK_ENABLE, unsigned long feature) + Enable a single feature specified in 'feature'. Can only operate on + one feature at a time. + +arch_prctl(ARCH_SHSTK_DISABLE, unsigned long feature) + Disable a single feature specified in 'feature'. Can only operate on + one feature at a time. + +arch_prctl(ARCH_SHSTK_LOCK, unsigned long features) + Lock in features at their current enabled or disabled status. 'features' + is a mask of all features to lock. All bits set are processed, unset bits + are ignored. The mask is ORed with the existing value. So any feature bits + set here cannot be enabled or disabled afterwards. + +The return values are as follows. On success, return 0. On error, errno can +be:: + + -EPERM if any of the passed feature are locked. + -ENOTSUPP if the feature is not supported by the hardware or + kernel. + -EINVAL arguments (non existing feature, etc) + +The feature's bits supported are:: + + ARCH_SHSTK_SHSTK - Shadow stack + ARCH_SHSTK_WRSS - WRSS + +Currently shadow stack and WRSS are supported via this interface. WRSS +can only be enabled with shadow stack, and is automatically disabled +if shadow stack is disabled. + +Proc Status +=========== +To check if an application is actually running with shadow stack, the +user can read the /proc/$PID/status. It will report "wrss" or "shstk" +depending on what is enabled. The lines look like this:: + + x86_Thread_features: shstk wrss + x86_Thread_features_locked: shstk wrss + +Implementation of the Shadow Stack +================================== + +Shadow Stack Size +----------------- + +A task's shadow stack is allocated from memory to a fixed size of +MIN(RLIMIT_STACK, 4 GB). In other words, the shadow stack is allocated to +the maximum size of the normal stack, but capped to 4 GB. In the case +of the clone3 syscall, there is a stack size passed in and shadow stack +uses this instead of the rlimit. + +Signal +------ + +The main program and its signal handlers use the same shadow stack. Because +the shadow stack stores only return addresses, a large shadow stack covers +the condition that both the program stack and the signal alternate stack run +out. + +When a signal happens, the old pre-signal state is pushed on the stack. When +shadow stack is enabled, the shadow stack specific state is pushed onto the +shadow stack. Today this is only the old SSP (shadow stack pointer), pushed +in a special format with bit 63 set. On sigreturn this old SSP token is +verified and restored by the kernel. The kernel will also push the normal +restorer address to the shadow stack to help userspace avoid a shadow stack +violation on the sigreturn path that goes through the restorer. + +So the shadow stack signal frame format is as follows:: + + |1...old SSP| - Pointer to old pre-signal ssp in sigframe token format + (bit 63 set to 1) + | ...| - Other state may be added in the future + + +32 bit ABI signals are not supported in shadow stack processes. Linux prevents +32 bit execution while shadow stack is enabled by the allocating shadow stacks +outside of the 32 bit address space. When execution enters 32 bit mode, either +via far call or returning to userspace, a #GP is generated by the hardware +which, will be delivered to the process as a segfault. When transitioning to +userspace the register's state will be as if the userspace ip being returned to +caused the segfault. + +Fork +---- + +The shadow stack's vma has VM_SHADOW_STACK flag set; its PTEs are required +to be read-only and dirty. When a shadow stack PTE is not RO and dirty, a +shadow access triggers a page fault with the shadow stack access bit set +in the page fault error code. + +When a task forks a child, its shadow stack PTEs are copied and both the +parent's and the child's shadow stack PTEs are cleared of the dirty bit. +Upon the next shadow stack access, the resulting shadow stack page fault +is handled by page copy/re-use. + +When a pthread child is created, the kernel allocates a new shadow stack +for the new thread. New shadow stack creation behaves like mmap() with respect +to ASLR behavior. Similarly, on thread exit the thread's shadow stack is +disabled. + +Exec +---- + +On exec, shadow stack features are disabled by the kernel. At which point, +userspace can choose to re-enable, or lock them.