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bh=Yr48j2bIPY5fAJkFuSojw587VB/8YMUbbc+kU0mekfQ=; b=RqWRh+b7rHwfPDY/JxEiOXYzrd7jefc8ec+SmrOrMF+gJqQSciCeq5yi ulgbzP6fukML/4nzrSS+KK2H9uQuCuM7Rl8C3FIcsgWI0va5JCAFdcUCT BW7TGdv+TtG4bPURV44m9q6luac1pFYiDrWaXtQ0eNa9vElj3vBFQdqBJ MT0NhT8YTOxhjN46+ngkh9ZiNti9CjfYJWy0zJp15Bvw5O7V1nEWcR80T qs1SAnAgSQVZVNVxi21sIyJjigZQSzTT/rWuV9D0+3IjlnZdsel84C2yj 6270NdlpKc70mFEYQI+XFZvKyk06INedNGEr2LZBE2YEPbFGtDBf6hCKN g==; X-IronPort-AV: E=McAfee;i="6600,9927,10675"; a="345969185" X-IronPort-AV: E=Sophos;i="5.98,333,1673942400"; d="scan'208";a="345969185" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2023 00:52:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10675"; a="681667638" X-IronPort-AV: E=Sophos;i="5.98,333,1673942400"; d="scan'208";a="681667638" Received: from yhuang6-mobl2.sh.intel.com ([10.238.7.50]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2023 00:52:40 -0700 From: Huang Ying To: Andrew Morton Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, Huang Ying , kernel test robot , Nadav Amit , Mel Gorman , Hugh Dickins , Matthew Wilcox , David Hildenbrand Subject: [PATCH] mm,unmap: avoid flushing TLB in batch if PTE is inaccessible Date: Mon, 10 Apr 2023 15:52:24 +0800 Message-Id: <20230410075224.827740-1-ying.huang@intel.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Queue-Id: 0A7FFC0002 X-Rspamd-Server: rspam01 X-Stat-Signature: r1sftsbj76ozrujhzny4gf4fd1ebofyp X-HE-Tag: 1681113164-460702 X-HE-Meta: U2FsdGVkX1//nI+7wNOeCrqZdxXjQjNASYZJ8CQFOnT8Ohnhvl4TNnwm4hPmo7UugsNH7grqPm7BDpX+CSxmDHtjDprvo6D7egz+9/k6Hj24Af94lN2VU62quxgWJ+K4JqpDt2GoCBtD41j+S/B6M5i0zj+svM4b5e1jpiZnlG6+4owaz5mo7xs/dDAhqKQW9q9gesmi1/SXKZYZBdm5vmrT0RSRNgsShUm2314xhO+Hg34HerPQPiEscC2stBkaOCn5JGBzS+gYvI7gW9pPToeaRXhp6YcngNMIBabjLxC8TPubxYyO8pfuUdUJQg0wc6Z9mG3x5JfI6syHFZcONvA0zhJzYm7WfGBWCfaCqtTTFUtAM1mY+gc6rhRlVdpCq0FxnEfMp1obMwtGv7yr0p33JNku6btYbtnqpzftj58MDZ+AjW1aHsrGzs/tU5m3r6JMPOmB4TDJoirOI7s3iYXdGHKdFiLK8Kmd7ByiWZpaYOickMFD6kLt/r3Dr0we5pismsoQnHtrgdiLvTSFmmmRoAKuHwjHP2tqrS2l2lh7MqRQmycs46hLYQ4TrrRjqur7NPFK+WTmy1j07osZpFBg+pBCx29r3g+UGRjiErE8OJOjXfDrNknEuTUke2xU5ZHDgL1fC21zH1ufrI9cRVfAcrS1sak9Q6rWyauKPsDLVXqRTfiZBipYum6r+UYZNuDHUlLe80VkIarT3rfXLuQp1n9dHXeO96Mh2WiBO8lINLTcDqsPb5TC8G8ihTGDpPo4uQajEJ37fF++JqT1cVU6sQf/v7Tz8JD55rxn1KXp2iqlbrgXRq5foowoZtv+ZjkrD3l3qjyA9tNFPKH6Db9x1Z6Y38DHQ41o2CG+ad+7cFe17At4+oKJoh3vdpTvf6giq1NXOtIniHhiexOQYpre66NgeijkQDIMzhfCb0yJTPgNrMQERKlZoefG/IPmLf1+QiMyPeswqqt9zXo tTZqsjQs QyztferIlws87rCv9ibWvCZVyxguJnADCIHJkGmtz6Fvdn9IxaL5N+3vvbKvT4ZezVo1gpKZWPhmscIbDnjUQGgejwULBkQcRkYGZSV+5niwpDtMANyVRWQDB1glanaWd6o18dknqxT/aSnYX1mV8/5o5YlTtJutlvaOtoxKJSumAMMspOi8B8Pqv6fAGnvtRiFMIUfoS5FxFTt3wzIwo8qsEAw37IXXMn3IG1SP1Oso7xyB73RvWjNK15krcX3+eypRqsQ6V3GwZ1bamXgfV1VqjSyo46XpXtkq/tCf8Sg0F6UfXe6ESkqX3F9EpoajS9NhJpAx1ELWRe2Z/wNyv3S+0xghRU15XqsNW2ElkcUWFjkaWKNnMzp/oQBZKGlXHiJR9Yqkaqn6dQvc2TSA6qLDR3QXIIQX4MkTIl2o91VWwoQs= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: 0Day/LKP reported a performance regression for commit 7e12beb8ca2a ("migrate_pages: batch flushing TLB"). In the commit, the TLB flushing during page migration is batched. So, in try_to_migrate_one(), ptep_clear_flush() is replaced with set_tlb_ubc_flush_pending(). In further investigation, it is found that the TLB flushing can be avoided in ptep_clear_flush() if the PTE is inaccessible. In fact, we can optimize in similar way for the batched TLB flushing too to improve the performance. So in this patch, we check pte_accessible() before set_tlb_ubc_flush_pending() in try_to_unmap/migrate_one(). Tests show that the benchmark score of the anon-cow-rand-mt test case of vm-scalability test suite can improve up to 2.1% with the patch on a Intel server machine. The TLB flushing IPI can reduce up to 44.3%. Link: https://lore.kernel.org/oe-lkp/202303192325.ecbaf968-yujie.liu@intel.com Link: https://lore.kernel.org/oe-lkp/ab92aaddf1b52ede15e2c608696c36765a2602c1.camel@intel.com/ Fixes: 7e12beb8ca2a ("migrate_pages: batch flushing TLB") Reported-by: kernel test robot Signed-off-by: "Huang, Ying" Cc: Nadav Amit Cc: Mel Gorman Cc: Hugh Dickins Cc: Matthew Wilcox (Oracle) Cc: David Hildenbrand Reviewed-by: Nadav Amit --- mm/rmap.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/mm/rmap.c b/mm/rmap.c index 8632e02661ac..3c7c43642d7c 100644 --- a/mm/rmap.c +++ b/mm/rmap.c @@ -1582,7 +1582,8 @@ static bool try_to_unmap_one(struct folio *folio, struct vm_area_struct *vma, */ pteval = ptep_get_and_clear(mm, address, pvmw.pte); - set_tlb_ubc_flush_pending(mm, pte_dirty(pteval)); + if (pte_accessible(mm, pteval)) + set_tlb_ubc_flush_pending(mm, pte_dirty(pteval)); } else { pteval = ptep_clear_flush(vma, address, pvmw.pte); } @@ -1963,7 +1964,8 @@ static bool try_to_migrate_one(struct folio *folio, struct vm_area_struct *vma, */ pteval = ptep_get_and_clear(mm, address, pvmw.pte); - set_tlb_ubc_flush_pending(mm, pte_dirty(pteval)); + if (pte_accessible(mm, pteval)) + set_tlb_ubc_flush_pending(mm, pte_dirty(pteval)); } else { pteval = ptep_clear_flush(vma, address, pvmw.pte); }